國立高雄大學圖資館 |

語系: 繁體中文

說明(常見問題)

圖資館首頁

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

Signal encoding and digital signal p...

Columbia University.

Signal encoding and digital signal processing in continuous time.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Signal encoding and digital signal processing in continuous time.
作者:	Kurchuk, Mariya.
面頁冊數:	298 p.
附註:	Source: Dissertation Abstracts International, Volume: 72-07, Section: B, page: .
附註:	Adviser: Yannis Tsividis.
Contained By:	Dissertation Abstracts International72-07B.
標題:	Engineering, Electronics and Electrical.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3453473
ISBN:	9781124615370

Signal encoding and digital signal processing in continuous time.
Kurchuk, Mariya.

Signal encoding and digital signal processing in continuous time. - 298 p.

Source: Dissertation Abstracts International, Volume: 72-07, Section: B, page: .

Thesis (Ph.D.)--Columbia University, 2011.

This work investigates signal encoding in, and architectures of, digital signal processing systems that function in continuous time (CT). Unlike conventional digital signal processors (DSPs), which rely on a clock to dictate the sampling times of an analog-to-digital converter (ADC) and to provide the tap delay timing, CT DSPs function entirely in continuous time, without a sampling or a synchronizing clock. The samples of a CT DSP system are generated and processed only when some measure of the input signal crosses a predetermined threshold. The effective sampling rate and the dynamic power dissipation of a CT digital system automatically adapt to the activity of the input signal. The properties of signals sampled in continuous time are investigated in this thesis. A technique for reducing the effective sampling rate of a CT system is presented, in which the digital signal encoding is varied by adjusting the resolution according to a property of the input. A variable-resolution system leads to a decrease in the number of samples generated, a reduction in the power dissipation and a reduction in the effective chip area of a CT DSP, all without sacrificing in-band performance. The properties of several asynchronous signal-driven sampling techniques are analyzed and compared.

ISBN: 9781124615370Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Signal encoding and digital signal processing in continuous time.
LDR:03203nmm 2200277 4500 001 309713
005 20111105132453.5
008 111212s2011 ||||||||||||||||| ||eng d
020 $a 9781124615370
035 $a (UMI)AAI3453473
035 $a AAI3453473
040 $a UMI $c UMI
100 1 $a Kurchuk, Mariya. $3 531046
245 1 0 $a Signal encoding and digital signal processing in continuous time.
300 $a 298 p.
500 $a Source: Dissertation Abstracts International, Volume: 72-07, Section: B, page: .
500 $a Adviser: Yannis Tsividis.
502 $a Thesis (Ph.D.)--Columbia University, 2011.
520 $a This work investigates signal encoding in, and architectures of, digital signal processing systems that function in continuous time (CT). Unlike conventional digital signal processors (DSPs), which rely on a clock to dictate the sampling times of an analog-to-digital converter (ADC) and to provide the tap delay timing, CT DSPs function entirely in continuous time, without a sampling or a synchronizing clock. The samples of a CT DSP system are generated and processed only when some measure of the input signal crosses a predetermined threshold. The effective sampling rate and the dynamic power dissipation of a CT digital system automatically adapt to the activity of the input signal. The properties of signals sampled in continuous time are investigated in this thesis. A technique for reducing the effective sampling rate of a CT system is presented, in which the digital signal encoding is varied by adjusting the resolution according to a property of the input. A variable-resolution system leads to a decrease in the number of samples generated, a reduction in the power dissipation and a reduction in the effective chip area of a CT DSP, all without sacrificing in-band performance. The properties of several asynchronous signal-driven sampling techniques are analyzed and compared.
520 $a The architecture and signal encoding of CT DSPs for signals in the lower gigahertz frequency range are investigated, with consideration of speed and accuracy limitations in the context of submicron CMOS technologies. A per-edge digital signal encoding technique is developed, which bypasses timing problems of processing high-speed digital signals; the properties of per-edge encoded signals are discussed. The design considerations of a low-resolution per-edge-encoded gigahertz-range CT DSP are discussed and an implementation for a possible application is detailed. A prototype chip has been fabricated in ST 65 nm CMOS technology, which has a compact processor core area of 0.073 mm 2. The implemented CT digital processor achieves SNDR of over 20 dB with 3 bits of resolution and a maximum usable -3dB bandwidth of 0.8 GHz to 3.2 GHz. The processor can be configured as a one-tap to six-tap CT FIR filter and has an active power dissipation that varies from 0.27 mW to 9.5 mW, depending on the amplitude and frequency of the input signal.
590 $a School code: 0054.
650 4 $a Engineering, Electronics and Electrical. $3 226981
690 $a 0544
710 2 $a Columbia University. $b Electrical Engineering. $3 531047
773 0 $t Dissertation Abstracts International $g 72-07B.
790 1 0 $a Tsividis, Yannis, $e advisor
790 $a 0054
791 $a Ph.D.
792 $a 2011
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3453473