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參材質/雙材質具氧化層基體絕緣結構之三閘極金氧半場效電晶體含氧化層介面缺...

國立高雄大學電機工程學系碩士班

參材質/雙材質具氧化層基體絕緣結構之三閘極金氧半場效電晶體含氧化層介面缺陷電荷之次臨界行為研究 = The Investigation on Subthreshold Behavior Model for the Tri-Material/Dual-Material SOI Triple-Gate MOSFETs with/without the Localized Interface Trapped Charges

紀錄類型:	書目-語言資料,印刷品 : 單行本
並列題名:	The Investigation on Subthreshold Behavior Model for the Tri-Material/Dual-Material SOI Triple-Gate MOSFETs with/without the Localized Interface Trapped Charges
作者:	張鐸瀚,
其他團體作者:	國立高雄大學
出版地:	[高雄市]
出版者:	撰者;
出版年:	2012[民101]
面頁冊數:	234面圖，表格 : 30公分;
標題:	雙材質三閘極金氧半場效電晶體
標題:	Tri-Material/Dual-Material Triple-Gate MOSFETs
電子資源:	http://handle.ncl.edu.tw/11296/ndltd/96508405759984231715
附註:	參考書目：面227-232
摘要註:	依據ITRS2009(International Technology of Roadmap for Semiconductor)報告，傳統平面電晶體(Planar Transistor)由於欠缺完好之短通道之控制特性，已無法因應未來高堆疊密度電路所需微小元件之要求，取而代之，為具良好短通道之控制行為;為與高堆疊密度之立體元件如雙閘極電晶體(Double-Gate MOSFET)、三閘極電晶體(Triple-Gate MOSFET)、四閘極電晶體(Four-Gate MOSFET)與環繞閘極電晶體(Surrounding-Gate MOSFET)。過去數十年來，雖然有研究關於平面單閘極電晶體與雙閘極電晶體之次臨界行為，但截至目前為止，相關之研究有關立體元件三閘極電晶體含氧化層缺陷介面電荷次臨界電特性仍相當欠缺，而針對植入帶電電荷改變電特性之記憶體元件(Charge Trapped or Injection Memory Device)應用而言，實有必要研究其次臨界行為特性與表面缺陷電荷之關係，並推導出可用之元件模型，以期該元件將來被有效應用於記憶體電路中。本論文乃基於帕森方程式之全二維解與全三維解，成功地推導出三閘極電晶體具氧化層基體絕緣結構之次臨界行為解析模型，此模型不僅準確顯示出電位分佈(potential distribution) 、電場分佈(electric field distribution) 、次臨界斜率(subthreshold slope)、次臨界電流(subthreshold current)、和臨界電壓縮減(threshold voltage degradation)、汲極偏壓導致能障降低(drain-induced-barrier-lowering, DIBL)等效應，而且此模型之演算結果與模擬數據相當接近，足以提供基本元件設計之導向，並進而被應用於積體電路設計之模擬。 ITRS2009 (International Technology of Roadmap for Semiconductor) has revealed that the conventional planar transistor is a lack of well-controlled short-channel effects and high packing density. With the strong field confinement, prominent volume conduction, and high packing density, the triple-gate MOSFETs that have demonstrated improved short-channel immunity and high driving currents can be the promising candidates for memory cells. A numerous of literatures have modeled the hot-carrier-induced threshold voltage of planar and double-gate MOSFETs in the past decade. Until now, there is no literature to investigate the subthreshold behavior model of the triple-gate MOSFETs with/without the localized interface trapped charges. With the application for Charge Trapped or Injection Memory Device, we report the 2D/3D analytical model of the subthreshold behavior for the triple-gate MOSFETs. In this thesis, based on the exact solution of the Poisson equation and perimeter- weighted-sum approach, an analytical subthreshold model for the triple-gate MOSFETs with/without localized interface trapped charges is developed by considering the effects of equivalent oxide charges on the flat-band voltage. The model explicitly shows the potential distribution, the electric field distribution, subthreshold slope, subthreshold current, threshold voltage roll-off, and drain-induced-barrier-lowing (DIBL) effect. The model is verified by the 2D/3D device simulator and can be efficiently used to investigate the hot-carrier-induced threshold voltage degradation of the advanced triple-gate MOSFETs charge-trapped memory device. This model not only gives the physical insights into the device physics but also offers the basic designing guidance of the SOI triple-gate transistor. Due to its computational efficiency, this model can be applied for SPICE simulation.

參材質/雙材質具氧化層基體絕緣結構之三閘極金氧半場效電晶體含氧化層介面缺陷電荷之次臨界行為研究 = The Investigation on Subthreshold Behavior Model for the Tri-Material/Dual-Material SOI Triple-Gate MOSFETs with/without the Localized Interface Trapped Charges
張, 鐸瀚

參材質/雙材質具氧化層基體絕緣結構之三閘極金氧半場效電晶體含氧化層介面缺陷電荷之次臨界行為研究 = The Investigation on Subthreshold Behavior Model for the Tri-Material/Dual-Material SOI Triple-Gate MOSFETs with/without the Localized Interface Trapped Charges / 張鐸瀚撰 - [高雄市] : 撰者, 2012[民101]. - 234面 ; 圖，表格 ; 30公分.
參考書目：面227-232.
雙材質三閘極金氧半場效電晶體Tri-Material/Dual-Material Triple-Gate MOSFETs

參材質/雙材質具氧化層基體絕緣結構之三閘極金氧半場效電晶體含氧化層介面缺陷電荷之次臨界行為研究 = The Investigation on Subthreshold Behavior Model for the Tri-Material/Dual-Material SOI Triple-Gate MOSFETs with/without the Localized Interface Trapped Charges
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