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DLL-based Fractional-N Frequency Syn...

Carleton University (Canada).

DLL-based Fractional-N Frequency Synthesizers.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	DLL-based Fractional-N Frequency Synthesizers.
作者:	Zarkeshvari, Farhad.
面頁冊數:	208 p.
附註:	Source: Dissertation Abstracts International, Volume: 73-12(E), Section: B.
Contained By:	Dissertation Abstracts International73-12B(E).
標題:	Engineering, Electronics and Electrical.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=NR87754
ISBN:	9780494877548

DLL-based Fractional-N Frequency Synthesizers.
Zarkeshvari, Farhad.

DLL-based Fractional-N Frequency Synthesizers. - 208 p.

Source: Dissertation Abstracts International, Volume: 73-12(E), Section: B.

Thesis (Ph.D.)--Carleton University (Canada), 2012.

Fractional-N phase locked loops (PLLs), widely used for clock/frequency generation in communication/digital systems, offer a frequency resolution tighter than their reference frequency. This work introduces an alternative delay locked loop (DLL) based fractional-N frequency/clock synthesizer and proposes a few architectures for it. A DLL-based synthesizer offers less close-in phase noise as it does not have the jitter accumulation problem of its PLL-based counterpart. Instead, a DLL-based synthesizer poses out-of-band spurious tones in its output frequency spectrum, a reference frequency away from main (carrier) frequency. The level of the spurious tones can be reduced by good design practice. A DLL-based synthesizer is most suitable for compact integration in complementary metal oxide semiconductor (CMOS) technology and can be competitive in terms of power consumption and controllability. The DLL-based fractional-N synthesizer is generally competitive with its PLL-based counterpart but it looks particularly appealing for applications sensitive to close-in phase noise and/or when a high quality LC oscillator (resonance oscillator using inductor and capacitor) is not affordable.

ISBN: 9780494877548Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

DLL-based Fractional-N Frequency Synthesizers.
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500 $a Source: Dissertation Abstracts International, Volume: 73-12(E), Section: B.
502 $a Thesis (Ph.D.)--Carleton University (Canada), 2012.
520 $a Fractional-N phase locked loops (PLLs), widely used for clock/frequency generation in communication/digital systems, offer a frequency resolution tighter than their reference frequency. This work introduces an alternative delay locked loop (DLL) based fractional-N frequency/clock synthesizer and proposes a few architectures for it. A DLL-based synthesizer offers less close-in phase noise as it does not have the jitter accumulation problem of its PLL-based counterpart. Instead, a DLL-based synthesizer poses out-of-band spurious tones in its output frequency spectrum, a reference frequency away from main (carrier) frequency. The level of the spurious tones can be reduced by good design practice. A DLL-based synthesizer is most suitable for compact integration in complementary metal oxide semiconductor (CMOS) technology and can be competitive in terms of power consumption and controllability. The DLL-based fractional-N synthesizer is generally competitive with its PLL-based counterpart but it looks particularly appealing for applications sensitive to close-in phase noise and/or when a high quality LC oscillator (resonance oscillator using inductor and capacitor) is not affordable.
520 $a This work also discusses implementation issues of a DLL-based fractional-N frequency synthesizer, explores different topologies and related circuit techniques for all the building blocks and describes associated trade-offs. At the circuit level, this research proposes two novel period synthesis techniques and a unique combination of a charge pump and a voltage to current converter for the delay locked loop.
520 $a A practical implementation targeting high-speed serial links applications in deep sub-micron technology is used as a test vehicle for proof of concept and to showcase the abilities and benefits of these architectures. Among the proposed architectures, the single loop one, with the best performance complexity trade-off and the ability of generating low spur levels for fractional multiplication factors close to an integer value is chosen for implementation. This proposed architecture equipped with a DeltaSigma modulator, phase interpolator based period synthesis, a differential dual compensated charge pump and a voltage to current converter to generate a fractional delay and achieves acceptable performance. The implemented synthesizer provides output frequencies between 4 GHz and 5GHz with total jitter less than 15ps when consuming about 11.5mW of power at a nominal supply voltage of 1V.
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