國立高雄大學圖資館 |

語系: 繁體中文

說明(常見問題)

圖資館首頁

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

噴霧熱裂解法製備N型氧化鋅於P型矽基板結構之研究 = Investiga...

周逸群

噴霧熱裂解法製備N型氧化鋅於P型矽基板結構之研究 = Investigation the structure of N-type ZnO fabricated on P-type Si Substrates by Spray Pyrolysis

紀錄類型:	書目-語言資料,印刷品 : 單行本
並列題名:	Investigation the structure of N-type ZnO fabricated on P-type Si Substrates by Spray Pyrolysis
作者:	周逸群,
其他團體作者:	國立高雄大學
出版地:	高雄市
出版者:	國立高雄大學;
出版年:	2013[民102]
面頁冊數:	109葉圖，表格 : 30公分;
標題:	噴霧熱裂解法
標題:	Spray Pyrolysis
電子資源:	https://hdl.handle.net/11296/bjdu7z
附註:	107年11月1日公開
附註:	參考書目：面103-109
摘要註:	本論文我們使用噴霧熱裂解法製備一層無刻意摻雜的氧化鋅於p型矽基板上，然後再成長一層低電阻率的銦氮共摻雜氧化鋅薄膜。主要的實驗變因是無摻雜氧化鋅層的沉積時間和熱處理溫度。在此我們先以表面和側面形貌以及結晶品質來分析樣品的特性。在銦氮共摻雜氧化鋅薄膜上做好電極即完成元件，元件可以經由電流-電壓的直流量測法得到電阻性記憶體的特性。當元件的無摻雜氧化鋅層沉積時間低於2.5分鐘時元件可以量測到從高電阻狀態轉換成低電阻狀態的現象，但無法再轉換回去；而當沉積時間高於5分鐘時元件的高低電阻狀態可以互相切換。高電阻狀態和低電阻狀態之間的最大電流比值出現在無摻雜氧化鋅層沉積15分鐘的樣品為5×10^3。之後我們藉由變溫的直流量測法去比較不同熱處理情形的無摻雜氧化鋅層的元件，並藉此分析載子傳輸的現象。 In this thesis we deposited the low resistivity Indium-Nitrogen co-doped ZnO thin film on p-type silicon substrates with a non-intensionally doped (ND) Zinc Oxide interlayer by spray pyrolysis. The deposition time and post heat treatment for the ND ZnO inter layer were studied. Film surface morphology and crystalline quality were characterized. After the metal contact formation with process, the device was formed. The devices show the resistive random-access memory (RRAM) character with the current-voltage measurement. With ND ZnO deposition time less than 2.5 min, the device can be transferred from initially high resistance state to low resistance state once and cannot be reinstated. With ND ZnO deposition time more than 5 min, the device can be transferred between the two states. The current ratio of low resistance state and high resistance state around 5×10^3 can be characterized for device with 15 min ND ZnO interlayer. The temperature dependent current voltage characteristics were carried out for these devices to realize the carrier transport behaviors for devices without and with post heat treatment process.

噴霧熱裂解法製備N型氧化鋅於P型矽基板結構之研究 = Investigation the structure of N-type ZnO fabricated on P-type Si Substrates by Spray Pyrolysis
周, 逸群

噴霧熱裂解法製備N型氧化鋅於P型矽基板結構之研究 = Investigation the structure of N-type ZnO fabricated on P-type Si Substrates by Spray Pyrolysis / 周逸群撰 - 高雄市 : 國立高雄大學, 2013[民102]. - 109葉 ; 圖，表格 ; 30公分.
107年11月1日公開參考書目：面103-109.
噴霧熱裂解法Spray Pyrolysis

噴霧熱裂解法製備N型氧化鋅於P型矽基板結構之研究 = Investigation the structure of N-type ZnO fabricated on P-type Si Substrates by Spray Pyrolysis
LDR:03346nam a2200277 450 001 389722
005 20190102102719.0
010 0 $b 精裝
010 0 $b 平裝
100 $a 20130926y2013 k y0chiy50 e
101 1 $a chi $d chi $d eng
102 $a tw
105 $a ak am 000yy
200 1 $a 噴霧熱裂解法製備N型氧化鋅於P型矽基板結構之研究 $d Investigation the structure of N-type ZnO fabricated on P-type Si Substrates by Spray Pyrolysis $z eng $f 周逸群撰
210 $a 高雄市 $c 國立高雄大學 $d 2013[民102]
215 0 $a 109葉 $c 圖，表格 $d 30公分
300 $a 107年11月1日公開
300 $a 參考書目：面103-109
314 $a 指導教授：藍文厚博士
328 $a 碩士論文--國立高雄大學電機工程學系碩士班
330 $a 本論文我們使用噴霧熱裂解法製備一層無刻意摻雜的氧化鋅於p型矽基板上，然後再成長一層低電阻率的銦氮共摻雜氧化鋅薄膜。主要的實驗變因是無摻雜氧化鋅層的沉積時間和熱處理溫度。在此我們先以表面和側面形貌以及結晶品質來分析樣品的特性。在銦氮共摻雜氧化鋅薄膜上做好電極即完成元件，元件可以經由電流-電壓的直流量測法得到電阻性記憶體的特性。當元件的無摻雜氧化鋅層沉積時間低於2.5分鐘時元件可以量測到從高電阻狀態轉換成低電阻狀態的現象，但無法再轉換回去；而當沉積時間高於5分鐘時元件的高低電阻狀態可以互相切換。高電阻狀態和低電阻狀態之間的最大電流比值出現在無摻雜氧化鋅層沉積15分鐘的樣品為5×10^3。之後我們藉由變溫的直流量測法去比較不同熱處理情形的無摻雜氧化鋅層的元件，並藉此分析載子傳輸的現象。 In this thesis we deposited the low resistivity Indium-Nitrogen co-doped ZnO thin film on p-type silicon substrates with a non-intensionally doped (ND) Zinc Oxide interlayer by spray pyrolysis. The deposition time and post heat treatment for the ND ZnO inter layer were studied. Film surface morphology and crystalline quality were characterized. After the metal contact formation with process, the device was formed. The devices show the resistive random-access memory (RRAM) character with the current-voltage measurement. With ND ZnO deposition time less than 2.5 min, the device can be transferred from initially high resistance state to low resistance state once and cannot be reinstated. With ND ZnO deposition time more than 5 min, the device can be transferred between the two states. The current ratio of low resistance state and high resistance state around 5×10^3 can be characterized for device with 15 min ND ZnO interlayer. The temperature dependent current voltage characteristics were carried out for these devices to realize the carrier transport behaviors for devices without and with post heat treatment process.
510 1 $a Investigation the structure of N-type ZnO fabricated on P-type Si Substrates by Spray Pyrolysis $z eng
610 # 0 $a 噴霧熱裂解法 $a 氧化鋅 $a 電阻性記憶體 $a 電流-電壓直流量測法 $a 載子傳輸
610 # 1 $a Spray Pyrolysis $a ZnO $a RRAM $a I-V measurement $a current transport
681 $a 008M/0019 $b 542201 7731 $v 2007年版
700 1 $a 周 $b 逸群 $4 撰 $3 614580
712 0 2 $a 國立高雄大學 $b 電機工程學系碩士班 $3 166118
801 0 $a tw $b NUK $c 20181115 $g CCR
856 7 # $u https://hdl.handle.net/11296/bjdu7z $z 電子資源 $2 http