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效能為尺寸相依的矽鍺應變通道電晶體 = Performance Depe...
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國立高雄大學電機工程學系碩士班
效能為尺寸相依的矽鍺應變通道電晶體 = Performance Dependent on Width-to-Length Ratio of Strained SiGe Channel MOSFETs
Record Type:
Language materials, printed : monographic
Paralel Title:
Performance Dependent on Width-to-Length Ratio of Strained SiGe Channel MOSFETs
Author:
林育生,
Secondary Intellectual Responsibility:
國立高雄大學
Place of Publication:
[高雄市]
Published:
撰者;
Year of Publication:
2013[民102]
Description:
66面圖,表格 : 30公分;
Subject:
金氧半場效電晶體
Subject:
CMOSFET
Online resource:
http://handle.ncl.edu.tw/11296/ndltd/04678437708719428166
Notes:
參考書目:面55-57
Notes:
102年10月31日公開
Summary:
本論文中所使用的實驗元件為65奈米高介電常數絕緣膜/金屬(High-k/metal)製程的矽鍺通道的金氧半場效電晶體(CMOSFET),通道結構分別是上面蓋有矽的矽鍺通道和純矽通道的兩種元件,矽鍺通道元件受到因為晶格常數差異而產生的雙軸壓縮應變,純矽的通道則沒有受到應變影響,做為通道受到應變前後的對比。在P型通道的量測結果中,發現雙軸壓縮應變對元件效能影響並非絕對,我們提出通道寬度與長度的比值,關係到由相對於通道縱向或是橫向配置來主導,由縱向與橫向壓阻係數的差異來解釋雙軸壓縮應變對於載子移載率的增強或衰減效果。以本論文中使用的所有樣本而言,當通道寬度除以通道長度比值很大時,受到雙軸壓縮應變<110> P型通道,會對電性產生衰退效果,而當通道寬度除以通道長度比值小於2.5,受到雙軸壓縮應變<110> P型通道,對電性的影響轉為正向,對電晶體效能有提升幫助。受到雙軸壓縮應變的N型通道,則較未受應變的通道,有衰退反應。 This thesis measures the n- and p-MOSFETs fabricated through 65 nm high k/metal gate CMOSFET process flow. The channels of the Si cap on SiGe were compared with Si-only channels. We found that biaxial compressive strain effect on device performance depends on channel width and channel length. The results indicate that a high W-L ratio in the <110> p-channel and n-channel can degradation performance of biaxial compressive stress. Meanwhile, a low W-L ratio in the p-channel can improve performance; but the ratio should at least be below 2.5 in this thesis. The dominance of the longitudinal or transverse configurations successfully explains this phenomenon because of the reliance of the different levels of piezoresistance coefficient on the channel orientation.
效能為尺寸相依的矽鍺應變通道電晶體 = Performance Dependent on Width-to-Length Ratio of Strained SiGe Channel MOSFETs
林, 育生
效能為尺寸相依的矽鍺應變通道電晶體
= Performance Dependent on Width-to-Length Ratio of Strained SiGe Channel MOSFETs / 林育生撰 - [高雄市] : 撰者, 2013[民102]. - 66面 ; 圖,表格 ; 30公分.
參考書目:面55-57102年10月31日公開.
金氧半場效電晶體CMOSFET
效能為尺寸相依的矽鍺應變通道電晶體 = Performance Dependent on Width-to-Length Ratio of Strained SiGe Channel MOSFETs
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本論文中所使用的實驗元件為65奈米高介電常數絕緣膜/金屬(High-k/metal)製程的矽鍺通道的金氧半場效電晶體(CMOSFET),通道結構分別是上面蓋有矽的矽鍺通道和純矽通道的兩種元件,矽鍺通道元件受到因為晶格常數差異而產生的雙軸壓縮應變,純矽的通道則沒有受到應變影響,做為通道受到應變前後的對比。在P型通道的量測結果中,發現雙軸壓縮應變對元件效能影響並非絕對,我們提出通道寬度與長度的比值,關係到由相對於通道縱向或是橫向配置來主導,由縱向與橫向壓阻係數的差異來解釋雙軸壓縮應變對於載子移載率的增強或衰減效果。以本論文中使用的所有樣本而言,當通道寬度除以通道長度比值很大時,受到雙軸壓縮應變<110> P型通道,會對電性產生衰退效果,而當通道寬度除以通道長度比值小於2.5,受到雙軸壓縮應變<110> P型通道,對電性的影響轉為正向,對電晶體效能有提升幫助。受到雙軸壓縮應變的N型通道,則較未受應變的通道,有衰退反應。 This thesis measures the n- and p-MOSFETs fabricated through 65 nm high k/metal gate CMOSFET process flow. The channels of the Si cap on SiGe were compared with Si-only channels. We found that biaxial compressive strain effect on device performance depends on channel width and channel length. The results indicate that a high W-L ratio in the <110> p-channel and n-channel can degradation performance of biaxial compressive stress. Meanwhile, a low W-L ratio in the p-channel can improve performance; but the ratio should at least be below 2.5 in this thesis. The dominance of the longitudinal or transverse configurations successfully explains this phenomenon because of the reliance of the different levels of piezoresistance coefficient on the channel orientation.
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http://handle.ncl.edu.tw/11296/ndltd/04678437708719428166
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