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High Speed DSP Circuits and Systems ...

Hsiao, Frank.

High Speed DSP Circuits and Systems for 60 GHz Wireless Communication.

Record Type:	Electronic resources : Monograph/item
Title/Author:	High Speed DSP Circuits and Systems for 60 GHz Wireless Communication.
Author:	Hsiao, Frank.
Description:	134 p.
Notes:	Source: Dissertation Abstracts International, Volume: 74-10(E), Section: B.
Notes:	Adviser: M.C. Frank Chang.
Contained By:	Dissertation Abstracts International74-10B(E).
Subject:	Engineering, Electronics and Electrical.
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3564376
ISBN:	9781303132070

High Speed DSP Circuits and Systems for 60 GHz Wireless Communication.
Hsiao, Frank.

High Speed DSP Circuits and Systems for 60 GHz Wireless Communication. - 134 p.

Source: Dissertation Abstracts International, Volume: 74-10(E), Section: B.

Thesis (Ph.D.)--University of California, Los Angeles, 2013.

The unlicensed 60 GHz band provides new opportunities for short ranged indoor Gb/s wireless communication applications. Compared with III-V semiconductor process technologies, nanometer CMOS based 60 GHz transceivers are attractive from the manufacturing cost and low power consumption point of view but these sensitive mm-Wave transceivers are highly susceptible to process variations thus they face a big challenge in achieving high yield performance. This suggests DSP based calibration circuits and algorithms to compensate for the performance loss due to process variations. In the first part of the dissertation, DSP based "Self-Healing" circuits and systems are presented to perform concurrent calibration on multiple RF transceiver parameters such as noise figure, image, transmitter IQ mismatch, and DC offset to optimize the 60 GHz CMOS transceiver performance. Digital baseband circuits applied to probe and measure the RF parameters such as direct digital frequency synthesizer, FFT based spectrum analyzer, and self-healing calibration controller will be discussed for a 4 Gb/s 60 GHz self-healing transceiver SOC in 65nm CMOS process.

ISBN: 9781303132070Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

High Speed DSP Circuits and Systems for 60 GHz Wireless Communication.
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100 1 $a Hsiao, Frank. $3 660306
245 1 0 $a High Speed DSP Circuits and Systems for 60 GHz Wireless Communication.
300 $a 134 p.
500 $a Source: Dissertation Abstracts International, Volume: 74-10(E), Section: B.
500 $a Adviser: M.C. Frank Chang.
502 $a Thesis (Ph.D.)--University of California, Los Angeles, 2013.
520 $a The unlicensed 60 GHz band provides new opportunities for short ranged indoor Gb/s wireless communication applications. Compared with III-V semiconductor process technologies, nanometer CMOS based 60 GHz transceivers are attractive from the manufacturing cost and low power consumption point of view but these sensitive mm-Wave transceivers are highly susceptible to process variations thus they face a big challenge in achieving high yield performance. This suggests DSP based calibration circuits and algorithms to compensate for the performance loss due to process variations. In the first part of the dissertation, DSP based "Self-Healing" circuits and systems are presented to perform concurrent calibration on multiple RF transceiver parameters such as noise figure, image, transmitter IQ mismatch, and DC offset to optimize the 60 GHz CMOS transceiver performance. Digital baseband circuits applied to probe and measure the RF parameters such as direct digital frequency synthesizer, FFT based spectrum analyzer, and self-healing calibration controller will be discussed for a 4 Gb/s 60 GHz self-healing transceiver SOC in 65nm CMOS process.
520 $a In the second part of the dissertation, the focus will be on the implementation aspects of a digital modem for a muti-Gb/s 60 GHz SOC radio. A 7 Gb/s OFDM/Single-Carrier frequency domain equalizer in 65 nm will be presented as an example. 4-parallel signal processing architecture allows this equalizer chip to achieve a symbol sampling rate of 1.76 GS/s while the core DSP circuits are clocked at 1/4 the input symbol rate. This equalizer chip is equipped with a 512pt FFT processor and a 512pt IFFT processor to demodulate the received OFDM and single-carrier signals. It includes a time domain Golay correlator based channel estimator to obtain the multipath channel impulse response, and it also includes a MMSE equalizer for channel correction in frequency domain.
590 $a School code: 0031.
650 4 $a Engineering, Electronics and Electrical. $3 226981
690 $a 0544
710 2 $a University of California, Los Angeles. $b Electrical Engineering 0303. $3 603261
773 0 $t Dissertation Abstracts International $g 74-10B(E).
790 $a 0031
791 $a Ph.D.
792 $a 2013
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3564376

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