國立高雄大學圖資館 |

語系: 繁體中文

說明(常見問題)

圖資館首頁

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

参閘極與環繞閘極金氧半場效電晶體含氧化層介面缺陷電荷與絕緣層堆疊結構之次...

國立高雄大學電機工程學系碩士班

参閘極與環繞閘極金氧半場效電晶體含氧化層介面缺陷電荷與絕緣層堆疊結構之次臨界行為研究 = The Investigation on Subthreshold Behavior Model for the Tri-Gate/Surrounding-Gate MOSFETs with the Interface Trapped Charges/Gate-Stack Structure

紀錄類型:	書目-語言資料,印刷品 : 單行本
並列題名:	The Investigation on Subthreshold Behavior Model for the Tri-Gate/Surrounding-Gate MOSFETs with the Interface Trapped Charges/Gate-Stack Structure
作者:	邱翊紘,
其他團體作者:	國立高雄大學
出版地:	[高雄市]
出版者:	撰者;
出版年:	2015[民104]
面頁冊數:	185面圖，表 : 30公分;
標題:	参閘極具堆疊結構金氧半場效電晶體
標題:	Tri-Material Gate-Stack Surrounding-Gate MOSFETs
電子資源:	http://handle.ncl.edu.tw/11296/ndltd/01078972898227108374
附註:	104年10月31日公開
附註:	參考書目：面164-170
摘要註:	本論文乃基於帕森方程式之拋物線近似與全二維解,成功地推導出参閘極與環繞閘極金氧半場效電晶體含氧化層介面缺陷電荷與絕緣層堆疊結構之次臨界行為解析模型,此模型顯示電位分佈(potential distribution) 、電場分佈(electric field distribution) 、次臨界斜率(subthreshold slope)、次臨界電流(subthreshold current)、和臨界電壓縮減(threshold voltage degradation)、汲極偏壓導致能障降低(drain-induced-barrier-lowering, DIBL)等效應。而且再藉由元件模擬軟體ISE-TCAD的輔助驗證,此模型之演算結果與模擬數據相當接近,它不僅可以給元件直觀的物理參數,還可以提供基本元件設計之導向,更進而應用於積體電路設計。為了將上述模型搭配非傳統的多重閘極、環繞閘極、複合材質閘極和具堆疊式結構的金氧半場效電晶體拓展到超低功耗的超大型積體電路應用上,吾人嘗試並且成功得到了環繞閘極與其参材質具堆疊式結構在類比和數位電路指標參數的模擬結果。此結果可以讓我們未來在建立各式元件所組成的電路模型得以驗證。 In this thesis, based on the parabolic approach and exact solution of the Poisson equation, an analytical subthreshold model for the tri-Gate/surrounding-gate MOSFETs with the interface trapped charges/gate-stack structure is developed. The model explicitly shows the potential distribution, the electric field distribution, subthreshold slope, subthreshold current, threshold voltage roll-off and drain-induced-barrier-lowing (DIBL) effect. The model is verified by the 2D/3D device simulator and can be efficiently used to investigate the hot-carrier-induced threshold voltage degradation of the advanced surrounding-gate MOSFETs charge-trapped memory device. This model not only gives the physical insights into the device physics but also offers the basic designing guidance of the SOI triple-gate transistor. Due to its computational efficiency, this model can be applied for SPICE simulation.In order to model the analog and digital performance of the circuit consist of multiple-gate MOSFET, it is necessary to know how to verify the model with simulator first. For this reason, we present the simulation results of the key parameters of analog and digital circuits.

参閘極與環繞閘極金氧半場效電晶體含氧化層介面缺陷電荷與絕緣層堆疊結構之次臨界行為研究 = The Investigation on Subthreshold Behavior Model for the Tri-Gate/Surrounding-Gate MOSFETs with the Interface Trapped Charges/Gate-Stack Structure
邱, 翊紘

参閘極與環繞閘極金氧半場效電晶體含氧化層介面缺陷電荷與絕緣層堆疊結構之次臨界行為研究 = The Investigation on Subthreshold Behavior Model for the Tri-Gate/Surrounding-Gate MOSFETs with the Interface Trapped Charges/Gate-Stack Structure / 邱翊紘撰 - [高雄市] : 撰者, 2015[民104]. - 185面 ; 圖，表 ; 30公分.
104年10月31日公開參考書目：面164-170.
参閘極具堆疊結構金氧半場效電晶體Tri-Material Gate-Stack Surrounding-Gate MOSFETs

参閘極與環繞閘極金氧半場效電晶體含氧化層介面缺陷電荷與絕緣層堆疊結構之次臨界行為研究 = The Investigation on Subthreshold Behavior Model for the Tri-Gate/Surrounding-Gate MOSFETs with the Interface Trapped Charges/Gate-Stack Structure
LDR:03895nam0a2200289 450 001 458446
005 20170214093214.0
009 458446
010 0 $b 精裝
010 0 $b 平裝
100 $a 20170214d2015 k y0chiy50 b
101 0 $a eng
102 $a tw
105 $a ak am 000yy
200 1 $a 参閘極與環繞閘極金氧半場效電晶體含氧化層介面缺陷電荷與絕緣層堆疊結構之次臨界行為研究 $d The Investigation on Subthreshold Behavior Model for the Tri-Gate/Surrounding-Gate MOSFETs with the Interface Trapped Charges/Gate-Stack Structure $z eng $f 邱翊紘撰
210 $a [高雄市] $c 撰者 $d 2015[民104]
215 0 $a 185面 $c 圖，表 $d 30公分
300 $a 104年10月31日公開
300 $a 參考書目：面164-170
314 $a 指導教授：江德光博士
328 $a 碩士論文--國立高雄大學電機工程學系碩士班
330 $a 本論文乃基於帕森方程式之拋物線近似與全二維解,成功地推導出参閘極與環繞閘極金氧半場效電晶體含氧化層介面缺陷電荷與絕緣層堆疊結構之次臨界行為解析模型,此模型顯示電位分佈(potential distribution) 、電場分佈(electric field distribution) 、次臨界斜率(subthreshold slope)、次臨界電流(subthreshold current)、和臨界電壓縮減(threshold voltage degradation)、汲極偏壓導致能障降低(drain-induced-barrier-lowering, DIBL)等效應。而且再藉由元件模擬軟體ISE-TCAD的輔助驗證,此模型之演算結果與模擬數據相當接近,它不僅可以給元件直觀的物理參數,還可以提供基本元件設計之導向,更進而應用於積體電路設計。為了將上述模型搭配非傳統的多重閘極、環繞閘極、複合材質閘極和具堆疊式結構的金氧半場效電晶體拓展到超低功耗的超大型積體電路應用上,吾人嘗試並且成功得到了環繞閘極與其参材質具堆疊式結構在類比和數位電路指標參數的模擬結果。此結果可以讓我們未來在建立各式元件所組成的電路模型得以驗證。 In this thesis, based on the parabolic approach and exact solution of the Poisson equation, an analytical subthreshold model for the tri-Gate/surrounding-gate MOSFETs with the interface trapped charges/gate-stack structure is developed. The model explicitly shows the potential distribution, the electric field distribution, subthreshold slope, subthreshold current, threshold voltage roll-off and drain-induced-barrier-lowing (DIBL) effect. The model is verified by the 2D/3D device simulator and can be efficiently used to investigate the hot-carrier-induced threshold voltage degradation of the advanced surrounding-gate MOSFETs charge-trapped memory device. This model not only gives the physical insights into the device physics but also offers the basic designing guidance of the SOI triple-gate transistor. Due to its computational efficiency, this model can be applied for SPICE simulation.In order to model the analog and digital performance of the circuit consist of multiple-gate MOSFET, it is necessary to know how to verify the model with simulator first. For this reason, we present the simulation results of the key parameters of analog and digital circuits.
510 1 $a The Investigation on Subthreshold Behavior Model for the Tri-Gate/Surrounding-Gate MOSFETs with the Interface Trapped Charges/Gate-Stack Structure $z eng
610 0 $a 参閘極具堆疊結構金氧半場效電晶體 $a 氧化層介面缺陷電荷 $a 短通道行為 $a 氧化層介面缺陷電荷引致次臨界行為衰減
610 1 $a Tri-Material Gate-Stack Surrounding-Gate MOSFETs $a Interface Trapped Charges $a Short-Channel Effect $a Interface-Trapped-Charge-Induced Subthreshold Be
681 $a 008M/0019 $b 542201 7702 $v 2007年版
700 1 $a 邱 $b 翊紘 $4 撰 $3 709686
712 0 2 $a 國立高雄大學 $b 電機工程學系碩士班 $3 166118
801 0 $a tw $b NUK $c 20151020 $g CCR
856 7 $z 電子資源 $2 http $u http://handle.ncl.edu.tw/11296/ndltd/01078972898227108374