| 摘要註: |
由於傳統平面電晶體(Planar Transistor)由於欠缺完好之短通道之控制特性,已無法因應未來高堆疊密度電路所需微小元件之要求,取而代之,為具良好短通道之控制行為與高堆疊密度之立體元件如雙閘極電晶體(Double-Gate MOSFET)、三閘極電晶體(Triple-Gate MOSFET)、四閘極電晶體(Four-Gate MOSFET) 、環繞閘極電晶體(Surrounding-Gate MOSFET)與Omega閘極電晶體(Omega-Gate MOSFET)。過去數十年來,雖然有研究關於平面單閘極電晶體與雙閘極電晶體之次臨界行為,但截至目前為止,相關之研究有關立體元件Omega閘極電晶體含氧化層缺陷介面電荷次臨界電特性仍相當欠缺,而針對植入帶電電荷改變電特性之記憶體元件(Charge Trapped or Injection Memory Device)應用而言,實有必要研究其次臨界行為特性與表面缺陷電荷之關係,並推導出可用之元件模型,以期該元件將來被有效應用於記憶體電路中。本論文乃基於帕森方程式之全二維解、微縮理論及周長加權近似法,成功地推導出Omega閘極電晶體具氧化層基體絕緣結構與Omega閘極電晶體具氧化層絕緣無接面(Junctionless)結構之次臨界行為解析模型,此模型不僅準確顯示出電位分佈(potential distribution) 、次臨界斜率(subthreshold slope)、次臨界電流(subthreshold current)、和臨界電壓縮減(threshold voltage degradation)、汲極偏壓導致能障降低(drain-induced-barrier-lowering, DIBL)等效應,而且此模型之演算結果與模擬數據相當接近,足以提供基本元件設計之導向,並且被應用在積體電路設計之模擬。最後再以Omega-Gate MOSFETs作為原件基礎組成簡單數位電路應用,利用此模擬的結果將有助於我們驗證日後推導出的元件電路模型。 Several studies have modeled the hot-carrier-induced threshold voltage of the planar MOSFETs in the past decade. The hot-carrier-induced positive or negative charges can be trapped in the interface between the gate oxide and the silicon film, which can cause the shift of the threshold voltage and deteriorate the electrical characteristic parameters of the device. Until now, there are few literatures to investigate the subthreshold behavior model of the ΩG MOSFETs with the localized trapped charges. With the application for Charge Trapped or Injection Memory Device, we report the quasi 2-D/Fully 2-D analytical model of the subthreshold behavior for the ΩG MOSFETs.In this thesis, based on the exact solution of the Poisson equation, scaling theory and perimeter-weighted-sum approach, an analytical subthreshold model for the ΩG MOSFETs with/without localized interface trapped charges is developed. The model explicitly shows the potential distribution, subthreshold slope, subthreshold current, threshold voltage, and drain-induced-barrier-lowing (DIBL) effect. The model is verified by the device simulator”DESSIS”, and can be efficiently used to investigate the hot-carrier-induced threshold voltage degradation of the advanced ΩG MOSFETs charge-trapped memory device. This model not only gives the physical insights into the device physics but also offers the basic designing guidance of the ΩG transistor. Due to its computational efficiency, this model can be applied for SPICE simulation. Finally, we also use the ΩG MOSFETs to simulate the simple digital circuits. The simulation results will be an important key to digital circuits in the future application. |