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多重鰭數與不同閘極製程對N型鰭式場效電晶體之電性分析及可靠度研究 = S...

國立高雄大學電機工程學系碩士班

多重鰭數與不同閘極製程對N型鰭式場效電晶體之電性分析及可靠度研究 = Study on Reliability of N-Channel FinFET Devices with Multi-Fin and Different Gate Processes

紀錄類型:	書目-語言資料,印刷品 : 單行本
並列題名:	Study on Reliability of N-Channel FinFET Devices with Multi-Fin and Different Gate Processes
作者:	鍾秉翰,
其他團體作者:	國立高雄大學
出版地:	[高雄市]
出版者:	撰者;
出版年:	2016[民105]
面頁冊數:	74面圖，表 : 30公分;
標題:	鰭式場效電晶體
標題:	FinFET
電子資源:	http://handle.ncl.edu.tw/11296/ndltd/84026507191986341643
附註:	105年3月31日公開
附註:	參考書目：面71-72
摘要註:	半導體元件正不斷往輕、薄、短、小的方向前進,而3D結構的FinFET被認為是突破傳統2D結構的新結構重大發現,根據目前研究指出3D結構的FinFet在未來可能取代傳統2D結構的電晶體。本篇論文主題是討論多重鰭數之FinFE在經由正偏壓不穩定效應(Positive Bias Temperature Instability)後的基本電性與可靠度之研究。以N-Type為例,在本研究中,我們發現Metal Gate TaN層厚度較薄的鰭式場效電晶體在電性上的表現上高於Metal Gate TaN層厚度較厚結構。接著我們利用Metal Gate TaN層厚度較厚與Metal Gate TaN層厚度較薄結構進行正偏壓不穩定效應,來分析元件退化狀況與機制。此時,我們發現到Metal Gate TaN層厚度較厚結構在PBTI的影響下,元件退化的情形較嚴重。有較高的臨界電壓、載子遷移率退化較為嚴重及較高的驅動電流。在使用time power law exponent 時間?公式得到n值可以看出Metal Gate TaN層厚度較厚結構與Metal Gate TaN層厚度較薄結構在給予不同閘極偏壓時,n值相近皆為0.2左右,皆傾向於氧化層缺陷,且Metal Gate TaN層厚度較厚結構受到閘極偏壓的影響較大。對於閘極Metal Gate TaN層厚度較厚結構,我們認為對元件通道的控制能力較差,在受到PBTI之後,元件特性的衰退情形較為嚴重,而Metal Gate TaN層厚度較薄結構可以為我們帶來較高的元件之可靠度。 Semiconductor devices have been continually improved to become lighter, thinner, shorter and smaller. In this field, the 3D-structure FinFET is considered as a technical breakthrough and stated by some researches as the possible devices to replace the traditional 2D-structure transistors. This thesis was centered on the basic electric measurement and reliability when the FinFET of MultipleFin undergoes the Positive Bias Temperature Instability.In case of N-Type, in this study, we found the electric property of thin FinFET in Metal Gate TaN layer performs better than the counterpart in thicker layer of Metal Gate TaN. Then the researchers applied both thinner and thicker layers of Metal Gate TaN to positive bias temperature instability (PBTI) test. Upon applying time power law exponent, researchers obtained a value "n" which indicates the thicker and thinner layers of Metal Gate TaN would be tended to oxide defects when under different gate voltages and the "n" value was approximately "0.2". The thicker layer of Metal Gate TaN could undertake more influence from gate voltages. For the thicker layer of Metal Gate TaN, the researchers suggested that gate voltages would be less able to influence device channel. However, the level of degeneration of elements would become more serious when the layer affected by PBTI. As a result, the thinner layer of Metal Gate TaN could provide higher element reliability.

多重鰭數與不同閘極製程對N型鰭式場效電晶體之電性分析及可靠度研究 = Study on Reliability of N-Channel FinFET Devices with Multi-Fin and Different Gate Processes
鍾, 秉翰

多重鰭數與不同閘極製程對N型鰭式場效電晶體之電性分析及可靠度研究 = Study on Reliability of N-Channel FinFET Devices with Multi-Fin and Different Gate Processes / 鍾秉翰撰 - [高雄市] : 撰者, 2016[民105]. - 74面 ; 圖，表 ; 30公分.
105年3月31日公開參考書目：面71-72.
鰭式場效電晶體FinFET

多重鰭數與不同閘極製程對N型鰭式場效電晶體之電性分析及可靠度研究 = Study on Reliability of N-Channel FinFET Devices with Multi-Fin and Different Gate Processes
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330 $a 半導體元件正不斷往輕、薄、短、小的方向前進,而3D結構的FinFET被認為是突破傳統2D結構的新結構重大發現,根據目前研究指出3D結構的FinFet在未來可能取代傳統2D結構的電晶體。本篇論文主題是討論多重鰭數之FinFE在經由正偏壓不穩定效應(Positive Bias Temperature Instability)後的基本電性與可靠度之研究。以N-Type為例,在本研究中,我們發現Metal Gate TaN層厚度較薄的鰭式場效電晶體在電性上的表現上高於Metal Gate TaN層厚度較厚結構。接著我們利用Metal Gate TaN層厚度較厚與Metal Gate TaN層厚度較薄結構進行正偏壓不穩定效應,來分析元件退化狀況與機制。此時,我們發現到Metal Gate TaN層厚度較厚結構在PBTI的影響下,元件退化的情形較嚴重。有較高的臨界電壓、載子遷移率退化較為嚴重及較高的驅動電流。在使用time power law exponent 時間?公式得到n值可以看出Metal Gate TaN層厚度較厚結構與Metal Gate TaN層厚度較薄結構在給予不同閘極偏壓時,n值相近皆為0.2左右,皆傾向於氧化層缺陷,且Metal Gate TaN層厚度較厚結構受到閘極偏壓的影響較大。對於閘極Metal Gate TaN層厚度較厚結構,我們認為對元件通道的控制能力較差,在受到PBTI之後,元件特性的衰退情形較為嚴重,而Metal Gate TaN層厚度較薄結構可以為我們帶來較高的元件之可靠度。 Semiconductor devices have been continually improved to become lighter, thinner, shorter and smaller. In this field, the 3D-structure FinFET is considered as a technical breakthrough and stated by some researches as the possible devices to replace the traditional 2D-structure transistors. This thesis was centered on the basic electric measurement and reliability when the FinFET of MultipleFin undergoes the Positive Bias Temperature Instability.In case of N-Type, in this study, we found the electric property of thin FinFET in Metal Gate TaN layer performs better than the counterpart in thicker layer of Metal Gate TaN. Then the researchers applied both thinner and thicker layers of Metal Gate TaN to positive bias temperature instability (PBTI) test. Upon applying time power law exponent, researchers obtained a value "n" which indicates the thicker and thinner layers of Metal Gate TaN would be tended to oxide defects when under different gate voltages and the "n" value was approximately "0.2". The thicker layer of Metal Gate TaN could undertake more influence from gate voltages. For the thicker layer of Metal Gate TaN, the researchers suggested that gate voltages would be less able to influence device channel. However, the level of degeneration of elements would become more serious when the layer affected by PBTI. As a result, the thinner layer of Metal Gate TaN could provide higher element reliability.
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