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Gain-cell embedded DRAMs for low-pow...

Meinerzhagen, Pascal.

Gain-cell embedded DRAMs for low-power VLSI systems-on-chip

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Gain-cell embedded DRAMs for low-power VLSI systems-on-chipby Pascal Meinerzhagen ... [et al.].
其他作者:	Meinerzhagen, Pascal.
出版者:	Cham :Springer International Publishing :2018.
面頁冊數:	ix, 146 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
標題:	Embedded computer systems.
電子資源:	http://dx.doi.org/10.1007/978-3-319-60402-2
ISBN:	9783319604022$q(electronic bk.)

Gain-cell embedded DRAMs for low-power VLSI systems-on-chip
Gain-cell embedded DRAMs for low-power VLSI systems-on-chip[electronic resource] /by Pascal Meinerzhagen ... [et al.]. - Cham :Springer International Publishing :2018. - ix, 146 p. :ill., digital ;24 cm.

Motivation -- Introduction to Gain-Cell Based eDRAMs (GC-eDRAMs) -- GC-eDRAMs Operated at Scaled Supply Voltages -- Near-VT GC-eDRAM Implementations with Extended Retention Times -- Aggressive Technology and Voltage Scaling (to Sub-VT Domain) -- Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications -- 4T Gain-Cell with Internal-Feedback for Ultra-Low Retention Power at Scaled CMOS Nodes -- Multilevel GC-eDRAM (MLGC-eDRAM) -- Soft Error Tolerant Low Power 4T Gain-Cell Array with Multi-Bit Error Detection and Correction -- Conclusions.

This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs) Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.

ISBN: 9783319604022$q(electronic bk.)

Standard No.: 10.1007/978-3-319-60402-2doiSubjects--Topical Terms:

184402
Embedded computer systems.

LC Class. No.: TK7895.E42

Dewey Class. No.: 006.22

Gain-cell embedded DRAMs for low-power VLSI systems-on-chip
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505 0 $a Motivation -- Introduction to Gain-Cell Based eDRAMs (GC-eDRAMs) -- GC-eDRAMs Operated at Scaled Supply Voltages -- Near-VT GC-eDRAM Implementations with Extended Retention Times -- Aggressive Technology and Voltage Scaling (to Sub-VT Domain) -- Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications -- 4T Gain-Cell with Internal-Feedback for Ultra-Low Retention Power at Scaled CMOS Nodes -- Multilevel GC-eDRAM (MLGC-eDRAM) -- Soft Error Tolerant Low Power 4T Gain-Cell Array with Multi-Bit Error Detection and Correction -- Conclusions.
520 $a This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs) Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
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