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RTL modeling with SystemVerilog for ...
~
Sutherland, Stuart, (1953-)
RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design /
紀錄類型:
書目-語言資料,印刷品 : Monograph/item
正題名/作者:
RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design /Stuart Sutherland.
其他題名:
RTL modeling with System Verilog for simulation and synthesis using System Verilog for ASIC and FPGA design
作者:
Sutherland, Stuart,
出版者:
Tualatin, OR :Sutherland HDL, Inc.,c2017.
面頁冊數:
xxxi, 453 p. :ill. ;23 cm.
標題:
Verilog (Computer hardware description language)
ISBN:
9781546776345 (pbk.) :
RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design /
Sutherland, Stuart,1953-
RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design /
RTL modeling with System Verilog for simulation and synthesis using System Verilog for ASIC and FPGA designStuart Sutherland. - Tualatin, OR :Sutherland HDL, Inc.,c2017. - xxxi, 453 p. :ill. ;23 cm.
Includes bibliographical references and index.
ISBN: 9781546776345 (pbk.) :$120Subjects--Topical Terms:
182774
Verilog (Computer hardware description language)
LC Class. No.: TK7885.7 / S966 2017
Dewey Class. No.: 621.392
RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design /
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