國立高雄大學圖資館 |

語系: 繁體中文

說明(常見問題)

圖資館首頁

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

Efficient design of variation-resili...

Dehaene, Wim.

Efficient design of variation-resilient ultra-low energy digital processors

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Efficient design of variation-resilient ultra-low energy digital processorsby Hans Reyserhove, Wim Dehaene.
作者:	Reyserhove, Hans.
其他作者:	Dehaene, Wim.
出版者:	Cham :Springer International Publishing :2019.
面頁冊數:	xxiv, 209 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
標題:	Integrated circuitsDesign and construction.
電子資源:	https://doi.org/10.1007/978-3-030-12485-4
ISBN:	9783030124854$q(electronic bk.)

Efficient design of variation-resilient ultra-low energy digital processors
Reyserhove, Hans.

Efficient design of variation-resilient ultra-low energy digital processors[electronic resource] /by Hans Reyserhove, Wim Dehaene. - Cham :Springer International Publishing :2019. - xxiv, 209 p. :ill., digital ;24 cm.

Chapter 1. Energy-Efficient Processors: Challenges and Solutions -- Chapter 2. Near-Threshold Operation: Technology, Building Blocks and Architecture -- Chapter 3. Efficient VLSI Design Flow -- Chapter 4. Ultra-Low Voltage Microcontrollers -- Chapter 5. Error Detection and Correction -- Chapter 6. Timing Error-Aware Microcontroller -- Chapter 7. Conclusion.

This book enables readers to achieve ultra-low energy digital system performance. The author's main focus is the energy consumption of microcontroller architectures in digital (sub)-systems. The book covers a broad range of topics extensively: from circuits through design strategy to system architectures. The result is a set of techniques and a context to realize minimum energy digital systems. Several prototype silicon implementations are discussed, which put the proposed techniques to the test. The achieved results demonstrate an extraordinary combination of variation-resilience, high speed performance and ultra-low energy. Presents a full bottom-up micro-electronics approach: circuit-level, design strategy and CAD automation, architecture optimization Motivates discussion with simulation results and/or measurements in an advanced nanometer CMOS process Compares traditional circuit/design/architecture techniques and state-of-the-art, setting the landscape of current best performance and how it can be improved.

ISBN: 9783030124854$q(electronic bk.)

Standard No.: 10.1007/978-3-030-12485-4doiSubjects--Topical Terms:

184690
Integrated circuits
--Design and construction.

LC Class. No.: TK7874 / .R49 2019

Dewey Class. No.: 621.3815

Efficient design of variation-resilient ultra-low energy digital processors
LDR:02380nmm a2200325 a 4500 001 554613
003 DE-He213
005 20190327173540.0
006 m d
007 cr nn 008maaau
008 191118s2019 gw s 0 eng d
020 $a 9783030124854$q(electronic bk.)
020 $a 9783030124847$q(paper)
024 7 $a 10.1007/978-3-030-12485-4 $2 doi
035 $a 978-3-030-12485-4
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7874 $b .R49 2019
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
090 $a TK7874 $b .R466 2019
100 1 $a Reyserhove, Hans. $3 836371
245 1 0 $a Efficient design of variation-resilient ultra-low energy digital processors $h [electronic resource] / $c by Hans Reyserhove, Wim Dehaene.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2019.
300 $a xxiv, 209 p. : $b ill., digital ; $c 24 cm.
505 0 $a Chapter 1. Energy-Efficient Processors: Challenges and Solutions -- Chapter 2. Near-Threshold Operation: Technology, Building Blocks and Architecture -- Chapter 3. Efficient VLSI Design Flow -- Chapter 4. Ultra-Low Voltage Microcontrollers -- Chapter 5. Error Detection and Correction -- Chapter 6. Timing Error-Aware Microcontroller -- Chapter 7. Conclusion.
520 $a This book enables readers to achieve ultra-low energy digital system performance. The author's main focus is the energy consumption of microcontroller architectures in digital (sub)-systems. The book covers a broad range of topics extensively: from circuits through design strategy to system architectures. The result is a set of techniques and a context to realize minimum energy digital systems. Several prototype silicon implementations are discussed, which put the proposed techniques to the test. The achieved results demonstrate an extraordinary combination of variation-resilience, high speed performance and ultra-low energy. Presents a full bottom-up micro-electronics approach: circuit-level, design strategy and CAD automation, architecture optimization Motivates discussion with simulation results and/or measurements in an advanced nanometer CMOS process Compares traditional circuit/design/architecture techniques and state-of-the-art, setting the landscape of current best performance and how it can be improved.
650 0 $a Integrated circuits $x Design and construction. $3 184690
650 1 4 $a Circuits and Systems. $3 274416
650 2 4 $a Signal, Image and Speech Processing. $3 273768
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 274412
700 1 $a Dehaene, Wim. $3 375733
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer eBooks
856 4 0 $u https://doi.org/10.1007/978-3-030-12485-4
950 $a Engineering (Springer-11647)