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Logic synthesis and SOC prototypingR...

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Logic synthesis and SOC prototypingRTL design using VHDL /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Logic synthesis and SOC prototypingby Vaibbhav Taraate.
其他題名:	RTL design using VHDL /
作者:	Taraate, Vaibbhav.
出版者:	Singapore :Springer Singapore :2020.
面頁冊數:	xix, 251 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
標題:	Systems on a chip.
電子資源:	https://doi.org/10.1007/978-981-15-1314-5
ISBN:	9789811513145$q(electronic bk.)

Logic synthesis and SOC prototypingRTL design using VHDL /
Taraate, Vaibbhav.

Logic synthesis and SOC prototypingRTL design using VHDL /[electronic resource] :by Vaibbhav Taraate. - Singapore :Springer Singapore :2020. - xix, 251 p. :ill., digital ;24 cm.

introduction -- ASiC Design and SOC prototype -- Design using VHDL & Guidelines -- Design using VHDL & Guidelines -- Design and Verification Strategies -- VHDL Design and RTL Tweaks -- ASiC Synthesis and Design Constraints -- Design optimization -- Design optimization -- FPGA for SOC Prototype -- Prototype using Single and Multiple FPGA.

This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. it covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASiC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.

ISBN: 9789811513145$q(electronic bk.)

Standard No.: 10.1007/978-981-15-1314-5doiSubjects--Topical Terms:

224012
Systems on a chip.

LC Class. No.: TK7895.E42 / T373 2020

Dewey Class. No.: 621.3815

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505 0 $a introduction -- ASiC Design and SOC prototype -- Design using VHDL & Guidelines -- Design using VHDL & Guidelines -- Design and Verification Strategies -- VHDL Design and RTL Tweaks -- ASiC Synthesis and Design Constraints -- Design optimization -- Design optimization -- FPGA for SOC Prototype -- Prototype using Single and Multiple FPGA.
520 $a This book describes RTL design, synthesis, and timing closure strategies for SOC blocks. it covers high-level RTL design scenarios and challenges for SOC design. The book gives practical information on the issues in SOC and ASiC prototyping using modern high-density FPGAs. The book covers SOC performance improvement techniques, testing, and system-level verification. The book also describes the modern Xilinx FPGA architecture and their use in SOC prototyping. The book covers the Synopsys DC, PT commands, and use of them to constraint and to optimize SOC design. The contents of this book will be of use to students, professionals, and hobbyists alike.
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