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Analog IC placement generation via n...

Gusmao, Antonio.

Analog IC placement generation via neural networks from unlabeled data

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Analog IC placement generation via neural networks from unlabeled databy Antonio Gusmao ... [et al.].
其他作者:	Gusmao, Antonio.
出版者:	Cham :Springer International Publishing :2020.
面頁冊數:	xiii, 87 p. :ill., digital ;24 cm.
Contained By:	Springer Nature eBook
標題:	Integrated circuits.
電子資源:	https://doi.org/10.1007/978-3-030-50061-0
ISBN:	9783030500610$q(electronic bk.)

Analog IC placement generation via neural networks from unlabeled data
Analog IC placement generation via neural networks from unlabeled data[electronic resource] /by Antonio Gusmao ... [et al.]. - Cham :Springer International Publishing :2020. - xiii, 87 p. :ill., digital ;24 cm. - SpringerBriefs in applied sciences and technology,2191-530X. - SpringerBriefs in applied sciences and technology..

Introduction -- Related Work: Machine Learning and Electronic Design Automation -- Unlabeled Data and Artificial Neural Networks -- Placement Loss: Placement Constraints Description and Satisfiability Evaluation -- Experimental Results in Industrial Case Studies -- Conclusions.

In this book, innovative research using artificial neural networks (ANNs) is conducted to automate the placement task in analog integrated circuit layout design, by creating a generalized model that can generate valid layouts at push-button speed. Further, it exploits ANNs' generalization and push-button speed prediction (once fully trained) capabilities, and details the optimal description of the input/output data relation. The description developed here is chiefly reflected in two of the system's characteristics: the shape of the input data and the minimized loss function. In order to address the latter, abstract and segmented descriptions of both the input data and the objective behavior are developed, which allow the model to identify, in newer scenarios, sub-blocks which can be found in the input data. This approach yields device-level descriptions of the input topology that, for each device, focus on describing its relation to every other device in the topology. By means of these descriptions, an unfamiliar overall topology can be broken down into devices that are subject to the same constraints as a device in one of the training topologies. In the experimental results chapter, the trained ANNs are used to produce a variety of valid placement solutions even beyond the scope of the training/validation sets, demonstrating the model's effectiveness in terms of identifying common components between newer topologies and reutilizing the acquired knowledge. Lastly, the methodology used can readily adapt to the given problem's context (high label production cost), resulting in an efficient, inexpensive and fast model.

ISBN: 9783030500610$q(electronic bk.)

Standard No.: 10.1007/978-3-030-50061-0doiSubjects--Topical Terms:

190434
Integrated circuits.

LC Class. No.: TK7874

Dewey Class. No.: 621.3815

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