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Completion detection in asynchronous circuitstoward solution of clock-related design challenges /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Completion detection in asynchronous circuitsby Pallavi Srivastava.
其他題名:	toward solution of clock-related design challenges /
作者:	Srivastava, Pallavi.
出版者:	Cham :Springer International Publishing :2022.
面頁冊數:	xv, 119 p. :ill. (chiefly color), digital ;24 cm.
Contained By:	Springer Nature eBook
標題:	Asynchronous circuitsDesign and construction.
電子資源:	https://doi.org/10.1007/978-3-031-18397-3
ISBN:	9783031183973$q(electronic bk.)

Completion detection in asynchronous circuitstoward solution of clock-related design challenges /
Srivastava, Pallavi.

Completion detection in asynchronous circuitstoward solution of clock-related design challenges /[electronic resource] :by Pallavi Srivastava. - Cham :Springer International Publishing :2022. - xv, 119 p. :ill. (chiefly color), digital ;24 cm.

Introduction to asynchronous circuit design -- "Preliminary considerations for asynchronous circuit design." -- "Completion detection schemes for asynchronous design style" -- Case Studies: Barrel shifter and binary adders -- "Generic Architecture of deterministic completion detection scheme" -- Architecture optimization using deterministic completion detection" -- Simulations.

This book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits. Analyzes circuit design techniques in the context of timing constraints; Develops a generic, deterministic completion detection scheme for asynchronous circuits using bundled data protocol; Demonstrates a single-precision, asynchronous bundled data barrel shifter to validate the completion detection scheme.

ISBN: 9783031183973$q(electronic bk.)

Standard No.: 10.1007/978-3-031-18397-3doiSubjects--Topical Terms:

224945
Asynchronous circuits
--Design and construction.

LC Class. No.: TK7868.A79

Dewey Class. No.: 621.3815

Completion detection in asynchronous circuitstoward solution of clock-related design challenges /
LDR:02586nmm a2200325 a 4500 001 633170
003 DE-He213
005 20221108201001.0
006 m d
007 cr nn 008maaau
008 230511s2022 sz s 0 eng d
020 $a 9783031183973$q(electronic bk.)
020 $a 9783031183966$q(paper)
024 7 $a 10.1007/978-3-031-18397-3 $2 doi
035 $a 978-3-031-18397-3
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7868.A79
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.3815 $2 23
090 $a TK7868.A79 $b S774 2022
100 1 $a Srivastava, Pallavi. $3 938943
245 1 0 $a Completion detection in asynchronous circuits $h [electronic resource] : $b toward solution of clock-related design challenges / $c by Pallavi Srivastava.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2022.
300 $a xv, 119 p. : $b ill. (chiefly color), digital ; $c 24 cm.
505 0 $a Introduction to asynchronous circuit design -- "Preliminary considerations for asynchronous circuit design." -- "Completion detection schemes for asynchronous design style" -- Case Studies: Barrel shifter and binary adders -- "Generic Architecture of deterministic completion detection scheme" -- Architecture optimization using deterministic completion detection" -- Simulations.
520 $a This book is intended for designers with experience in traditional (clocked) circuit design, seeking information about asynchronous circuit design, in order to determine if it would be advantageous to adopt asynchronous methodologies in their next design project. The author introduces a generic approach for implementing a deterministic completion detection scheme for asynchronous bundled data circuits that incorporates a data-dependent computational process, taking advantage of the average-case delay. The author validates the architecture using a barrel shifter, as shifting is the basic operation required by all the processors. The generic architecture proposed in this book for a deterministic completion detection scheme for bundled data circuits will facilitate researchers in considering the asynchronous design style for developing digital circuits. Analyzes circuit design techniques in the context of timing constraints; Develops a generic, deterministic completion detection scheme for asynchronous circuits using bundled data protocol; Demonstrates a single-precision, asynchronous bundled data barrel shifter to validate the completion detection scheme.
650 0 $a Asynchronous circuits $x Design and construction. $3 224945
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer Nature eBook
856 4 0 $u https://doi.org/10.1007/978-3-031-18397-3
950 $a Computer Science (SpringerNature-11645)