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Design through Verilog HDL /

~

Padmanabhan, T. R.

Design through Verilog HDL /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	Design through Verilog HDL /T.R. Padmanabhan, B. Bala Tripura Sundari.
作者:	Padmanabhan, T. R.
其他作者:	Tripura Sundari, B. Bala.
出版者:	Hoboken, NJ :IEEE Press ;c2004.
面頁冊數:	xii, 455 p. :ill. ;25 cm.
標題:	Verilog (Computer hardware description language)
電子資源:	http://www.loc.gov/catdir/toc/wiley032/2003057671.html
電子資源:	http://www.loc.gov/catdir/bios/wiley046/2003057671.html
電子資源:	http://www.loc.gov/catdir/description/wiley039/2003057671.html
ISBN:	0471441481 :

Design through Verilog HDL /
Padmanabhan, T. R.

Design through Verilog HDL /T.R. Padmanabhan, B. Bala Tripura Sundari. - Hoboken, NJ :IEEE Press ;c2004. - xii, 455 p. :ill. ;25 cm.

Includes bibliographical references (p. 449-450) and index.

ISBN: 0471441481 :NT1220

LCCN: 2003057671Subjects--Topical Terms:

182774
Verilog (Computer hardware description language)

LC Class. No.: TK7885.7 / .P37 2004

Dewey Class. No.: 621.39/2

Design through Verilog HDL /
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245 1 0 $a Design through Verilog HDL / $c T.R. Padmanabhan, B. Bala Tripura Sundari.
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300 $a xii, 455 p. : $b ill. ; $c 25 cm.
504 $a Includes bibliographical references (p. 449-450) and index.
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856 4 1 $3 Table of contents $u http://www.loc.gov/catdir/toc/wiley032/2003057671.html $z http://www.loc.gov/catdir/toc/wiley032/2003057671.html
856 4 2 $3 Contributor biographical information $u http://www.loc.gov/catdir/bios/wiley046/2003057671.html $z http://www.loc.gov/catdir/bios/wiley046/2003057671.html
856 4 2 $3 Publisher description $u http://www.loc.gov/catdir/description/wiley039/2003057671.html $z http://www.loc.gov/catdir/description/wiley039/2003057671.html

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http://www.loc.gov/catdir/toc/wiley032/2003057671.html
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http://www.loc.gov/catdir/description/wiley039/2003057671.html

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