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Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors.
Author:	Greene, Brian Joseph.
Description:	146 p.
Notes:	Advisers: James F. Gibbons; Judy L. Hoyt.
Notes:	Source: Dissertation Abstracts International, Volume: 64-09, Section: B, page: 4519.
Contained By:	Dissertation Abstracts International64-09B.
Subject:	Engineering, Electronics and Electrical.
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3104232
ISBN:	0496518003

Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors.
Greene, Brian Joseph.

Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors. [electronic resource] - 146 p.

Advisers: James F. Gibbons; Judy L. Hoyt.

Thesis (Ph.D.)--Stanford University, 2003.

For sub-50 nm gate length MOSFET fabrication, an SOI thickness on the order of 10 nm will be required. One limitation of the LSPE process has been the need for thick films (0.5--2 mum) and/or heavy P doping (10 19--1020 cm-3) to increase the maximum achievable lateral growth distance, and therefore minimize the area on the substrate occupied by seed holes. This dissertation discusses the characterization and optimization of process conditions for large area LSPE silicon film growth, as well as efforts to adapt the traditional LSPE process to achieve ultra-thin SOI layers (Tsilicon ≤ 25 nm) while avoiding the use of heavy active doping layers. MOSFETs fabricated in these films that exhibit electron mobility comparable to the Universal Si MOS Mobility are described.

ISBN: 0496518003Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors.
LDR:02833nmm _2200277 _450 001 162171
005 20051017073418.5
008 230606s2003 eng d
020 $a 0496518003
035 $a 00148672
035 $a 162171
040 $a UnM $c UnM
100 0 $a Greene, Brian Joseph. $3 227288
245 1 0 $a Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors. $h [electronic resource]
300 $a 146 p.
500 $a Advisers: James F. Gibbons; Judy L. Hoyt.
500 $a Source: Dissertation Abstracts International, Volume: 64-09, Section: B, page: 4519.
502 $a Thesis (Ph.D.)--Stanford University, 2003.
520 # $a For sub-50 nm gate length MOSFET fabrication, an SOI thickness on the order of 10 nm will be required. One limitation of the LSPE process has been the need for thick films (0.5--2 mum) and/or heavy P doping (10 19--1020 cm-3) to increase the maximum achievable lateral growth distance, and therefore minimize the area on the substrate occupied by seed holes. This dissertation discusses the characterization and optimization of process conditions for large area LSPE silicon film growth, as well as efforts to adapt the traditional LSPE process to achieve ultra-thin SOI layers (Tsilicon ≤ 25 nm) while avoiding the use of heavy active doping layers. MOSFETs fabricated in these films that exhibit electron mobility comparable to the Universal Si MOS Mobility are described.
520 # $a Thin film silicon on insulator fabrication is an increasingly important technology requirement for improving performance in future generation devices and circuits. One process for SOI fabrication that has recently been generating renewed interest is Lateral Solid Phase Epitaxy (LSPE) of silicon over oxide. This process involves annealing amorphous silicon that has been deposited on oxide patterned Si wafers. The (001) Si substrate forms the crystalline seed for epitaxial growth, permitting the generation of Si films that are both single crystal, and oriented to the substrate. This method is particularly attractive to fabrication that requires low temperature processing, because the Si films are deposited in the amorphous phase at temperatures near 525°C, and crystallized at temperatures near 570°C. It is also attractive for applications requiring three dimensional stacking of active silicon device layers, due to the relatively low temperatures involved.
590 $a School code: 0212.
650 # 0 $a Engineering, Electronics and Electrical. $3 226981
650 # 0 $a Engineering, Materials Science. $3 226940
710 0 # $a Stanford University. $3 212607
773 0 # $g 64-09B. $t Dissertation Abstracts International
790 $a 0212
790 1 0 $a Gibbons, James F., $e advisor
790 1 0 $a Hoyt, Judy L., $e advisor
791 $a Ph.D.
792 $a 2003
856 4 0 $u http://libsw.nuk.edu.tw/login?url=http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3104232 $z http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3104232