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Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors.
作者:	Greene, Brian Joseph.
面頁冊數:	146 p.
附註:	Advisers: James F. Gibbons; Judy L. Hoyt.
附註:	Source: Dissertation Abstracts International, Volume: 64-09, Section: B, page: 4519.
Contained By:	Dissertation Abstracts International64-09B.
標題:	Engineering, Electronics and Electrical.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3104232
ISBN:	0496518003

Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors.
Greene, Brian Joseph.

Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors. [electronic resource] - 146 p.

Advisers: James F. Gibbons; Judy L. Hoyt.

Thesis (Ph.D.)--Stanford University, 2003.

For sub-50 nm gate length MOSFET fabrication, an SOI thickness on the order of 10 nm will be required. One limitation of the LSPE process has been the need for thick films (0.5--2 mum) and/or heavy P doping (10 19--1020 cm-3) to increase the maximum achievable lateral growth distance, and therefore minimize the area on the substrate occupied by seed holes. This dissertation discusses the characterization and optimization of process conditions for large area LSPE silicon film growth, as well as efforts to adapt the traditional LSPE process to achieve ultra-thin SOI layers (Tsilicon ≤ 25 nm) while avoiding the use of heavy active doping layers. MOSFETs fabricated in these films that exhibit electron mobility comparable to the Universal Si MOS Mobility are described.

ISBN: 0496518003Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors.
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520 # $a For sub-50 nm gate length MOSFET fabrication, an SOI thickness on the order of 10 nm will be required. One limitation of the LSPE process has been the need for thick films (0.5--2 mum) and/or heavy P doping (10 19--1020 cm-3) to increase the maximum achievable lateral growth distance, and therefore minimize the area on the substrate occupied by seed holes. This dissertation discusses the characterization and optimization of process conditions for large area LSPE silicon film growth, as well as efforts to adapt the traditional LSPE process to achieve ultra-thin SOI layers (Tsilicon ≤ 25 nm) while avoiding the use of heavy active doping layers. MOSFETs fabricated in these films that exhibit electron mobility comparable to the Universal Si MOS Mobility are described.
520 # $a Thin film silicon on insulator fabrication is an increasingly important technology requirement for improving performance in future generation devices and circuits. One process for SOI fabrication that has recently been generating renewed interest is Lateral Solid Phase Epitaxy (LSPE) of silicon over oxide. This process involves annealing amorphous silicon that has been deposited on oxide patterned Si wafers. The (001) Si substrate forms the crystalline seed for epitaxial growth, permitting the generation of Si films that are both single crystal, and oriented to the substrate. This method is particularly attractive to fabrication that requires low temperature processing, because the Si films are deposited in the amorphous phase at temperatures near 525°C, and crystallized at temperatures near 570°C. It is also attractive for applications requiring three dimensional stacking of active silicon device layers, due to the relatively low temperatures involved.
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