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Tomography as a metrology technique for semiconductor manufacturing.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Tomography as a metrology technique for semiconductor manufacturing.
Author:	Kruger, Michiel Victor Paul.
Description:	143 p.
Notes:	Chairs: Kameshwar Poolla; Costas J. Spanos.
Notes:	Source: Dissertation Abstracts International, Volume: 64-09, Section: B, page: 4581.
Contained By:	Dissertation Abstracts International64-09B.
Subject:	Engineering, Mechanical.
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3105279
ISBN:	0496528467

Tomography as a metrology technique for semiconductor manufacturing.
Kruger, Michiel Victor Paul.

Tomography as a metrology technique for semiconductor manufacturing. [electronic resource] - 143 p.

Chairs: Kameshwar Poolla; Costas J. Spanos.

Thesis (Ph.D.)--University of California, Berkeley, 2003.

In this thesis, we first discuss the status quo of metrology methods in use in the semiconductor manufacturing industry. This discussion is followed by a thorough introduction to Electrical Impedance Tomography. We then argue that Electrical Impedance Tomography can be a compelling technique to obtain spatially and time-resolved wafer state information during wafer processing. To illustrate these ideas, we design and analyze two EIT based sensors for use during semiconductor manufacturing.

ISBN: 0496528467Subjects--Topical Terms:

212470
Engineering, Mechanical.

Tomography as a metrology technique for semiconductor manufacturing.
LDR:03553nmm _2200313 _450 001 162204
005 20051017073421.5
008 230606s2003 eng d
020 $a 0496528467
035 $a 00148705
035 $a 162204
040 $a UnM $c UnM
100 0 $a Kruger, Michiel Victor Paul. $3 227324
245 1 0 $a Tomography as a metrology technique for semiconductor manufacturing. $h [electronic resource]
300 $a 143 p.
500 $a Chairs: Kameshwar Poolla; Costas J. Spanos.
500 $a Source: Dissertation Abstracts International, Volume: 64-09, Section: B, page: 4581.
502 $a Thesis (Ph.D.)--University of California, Berkeley, 2003.
520 # $a In this thesis, we first discuss the status quo of metrology methods in use in the semiconductor manufacturing industry. This discussion is followed by a thorough introduction to Electrical Impedance Tomography. We then argue that Electrical Impedance Tomography can be a compelling technique to obtain spatially and time-resolved wafer state information during wafer processing. To illustrate these ideas, we design and analyze two EIT based sensors for use during semiconductor manufacturing.
520 # $a Next, we propose a novel EIT based sensor which can provide temporal and spatial wafer surface potential information during plasma processing. Our design relies on a resistive network containing discrete transduction elements whose conductivity is modulated by the variable of interest. To assess our idea, we performed simulation studies on a prototype sensor which uses depletion mode NMOSFETs as transduction elements. We have obtained promising simulation results with this novel EIT based metrology technique.
520 # $a Our first sensor is a device to measure etch rates or film thicknesses. We have designed, fabricated and tested this sensor. We use standard EIT techniques to estimate the conductivity distribution of a thin film of conductive polysilicon across a wafer. The estimated conductivity distribution can, in turn, be related to the thickness of the polysilicon film from first principles. Differential thickness measurements from our prototype etch rate sensor correlate very well with optical thickness measurements.
520 # $a The basic idea of Electrical Impedance Tomography is to image the conductivity distribution in the interior of a conductive object by performing simple electrical measurements on the periphery of the object. In a semiconductor manufacturing context, physical and chemical effects during semiconductor manufacturing can induce a change in conductivity in the interior of a wafer. EIT techniques can be used to infer these conductivity changes. In turn, these changes can be related to the physical and chemical effects using appropriate models.
520 # $a This dissertation is concerned with exploring the feasibility of a class of sensors which provide temporally and spatially resolved wafer state information during semiconductor manufacturing. The common theme shared by this class of sensors is that they are based on Electrical Impedance Tomography (EIT). EIT is a non-destructive in vivo imaging technique principally used in medical applications.
590 $a School code: 0028.
650 # 0 $a Engineering, Mechanical. $3 212470
650 # 0 $a Engineering, Electronics and Electrical. $3 226981
710 0 # $a University of California, Berkeley. $3 212474
773 0 # $g 64-09B. $t Dissertation Abstracts International
790 $a 0028
790 1 0 $a Poolla, Kameshwar, $e advisor
790 1 0 $a Spanos, Costas J., $e advisor
791 $a Ph.D.
792 $a 2003
856 4 0 $u http://libsw.nuk.edu.tw/login?url=http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3105279 $z http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3105279