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The test and diagnosis of FPGAs

Record Type:	Electronic resources : Monograph/item
Title/Author:	The test and diagnosis of FPGAs
Author:	Chmelar, Erik.
Description:	92 p.
Notes:	Adviser: Edward J. McCluskey.
Notes:	Source: Dissertation Abstracts International, Volume: 65-04, Section: B, page: 2007.
Contained By:	Dissertation Abstracts International65-04B.
Subject:	Engineering, Electronics and Electrical.
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3128365
ISBN:	0496756273

The test and diagnosis of FPGAs
Chmelar, Erik.

The test and diagnosis of FPGAs [electronic resource] - 92 p.

Adviser: Edward J. McCluskey.

Thesis (Ph.D.)--Stanford University, 2004.

A Field programmable Gate Array (FPGA) is a configurable integrated circuit that can implement an arbitrary logic design. However, because integrated circuit manufacturing is imperfect, defects occur. To cope with defects, which cause an FPGA to function incorrectly, the manufacturer must execute two essential tasks: (1) thorough test to ensure high device quality, and (2) efficient diagnosis to achieve high manufacturing yield. Because of the distinct architectural and functional differences between non-configurable circuits like Application-speck Integrated Circuits (ASICs) and configurable circuits like FPGAs, many of the test and diagnosis techniques for ASICs are not applicable to FPGAs. Additionally, the configurable interconnection network, which constitutes up to 80% of the die area and up to 8 metal layers, poses the primary challenge to FPGA test and diagnosis since numerous signal paths (hundreds or more) can be configured between a single pair of logic elements, each of which may be faulty.

ISBN: 0496756273Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

The test and diagnosis of FPGAs
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520 # $a A Field programmable Gate Array (FPGA) is a configurable integrated circuit that can implement an arbitrary logic design. However, because integrated circuit manufacturing is imperfect, defects occur. To cope with defects, which cause an FPGA to function incorrectly, the manufacturer must execute two essential tasks: (1) thorough test to ensure high device quality, and (2) efficient diagnosis to achieve high manufacturing yield. Because of the distinct architectural and functional differences between non-configurable circuits like Application-speck Integrated Circuits (ASICs) and configurable circuits like FPGAs, many of the test and diagnosis techniques for ASICs are not applicable to FPGAs. Additionally, the configurable interconnection network, which constitutes up to 80% of the die area and up to 8 metal layers, poses the primary challenge to FPGA test and diagnosis since numerous signal paths (hundreds or more) can be configured between a single pair of logic elements, each of which may be faulty.
520 # $a Instead of considering the configurability of an FPGA a burden that must be circumvented to effectively test or diagnose the device, it can be considered a tool to enhance test and diagnosis. This dissertation presents several new and effective test and diagnosis techniques that take advantage of this configurability. The purpose of test is to detect defects. Three test techniques are presented: (1) a delay fault test that detects very small (nanosecond) delay faults using slow (inexpensive) Automated Test Equipment (ATE), (2) a differential IDDQ bridge fault test that cancels a large portion of the device leakage current to more easily observe a small fault current, and (3) a Design for Test (DFT) technique that significantly reduces the configuration time, and therefore test time, of an FPGA. The purpose of diagnosis is to locate or identify defects. Two diagnosis techniques are presented: (1) a bridge fault location technique that employs differential IDDQ to locate a bridge fault, and (2) an automated stuck-at fault diagnosis technique that significantly reduces the diagnosis time. Each technique is described in detail, including both the advantages over the previous techniques and experimental results.
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