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Design of CMOS receivers for paralle...

Emami-Neyestanak, Azita.

Design of CMOS receivers for parallel optical interconnects.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Design of CMOS receivers for parallel optical interconnects.
作者:	Emami-Neyestanak, Azita.
面頁冊數:	127 p.
附註:	Adviser: Mark A. Horowitz.
附註:	Source: Dissertation Abstracts International, Volume: 65-09, Section: B, page: 4732.
Contained By:	Dissertation Abstracts International65-09B.
標題:	Engineering, Electronics and Electrical.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3145503
ISBN:	0496044095

Design of CMOS receivers for parallel optical interconnects.
Emami-Neyestanak, Azita.

Design of CMOS receivers for parallel optical interconnects. - 127 p.

Adviser: Mark A. Horowitz.

Thesis (Ph.D.)--Stanford University, 2004.

The growing demand for high-bandwidth communication between integrated circuits calls for large numbers of high-speed inputs and outputs (IOs) per chip. IO data rates have increased to the point where electrical signaling is now limited by the channel properties. In order to achieve multi-Gb/s data rates, complex designs that equalize the channel are necessary.

ISBN: 0496044095Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Design of CMOS receivers for parallel optical interconnects.
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502 $a Thesis (Ph.D.)--Stanford University, 2004.
520 # $a The growing demand for high-bandwidth communication between integrated circuits calls for large numbers of high-speed inputs and outputs (IOs) per chip. IO data rates have increased to the point where electrical signaling is now limited by the channel properties. In order to achieve multi-Gb/s data rates, complex designs that equalize the channel are necessary.
520 # $a The synchronized receive clock can be generated in many ways. While the standard oversampled clock recovery is possible, it needs extra clock phases in the middle of main data samples. In order to reduce the power, a baud rate clock recovery technique is proposed and implemented as part of a transceiver array test-chip. The resulting transceiver consumes less than 150mW per channel at 5.OGb/s in a 025mum CMOS technology. If projected to a 90nm CMOS technology, 15Gb/s data rate and 30mW power per IO are possible, which allow more than 10Tb/s chip-to-chip band-width, with up to one thousand IOs per chip.
520 # $a Using optics for chip-to-chip interconnections is promising since the optical channel dispersion and cross-talk are small. In this work we demonstrate the possibility of building small and low-power optical receivers that facilitate large numbers of IOs. A new double sampling/integrating front-end is proposed and implemented. Unlike prior designs, this receiver removes the need for a gain stage that runs at the data rate, making it suitable for low-power implementations. This front-end allows a time-division multiplexing technique to support very high data rates. The dynamic range of the integrating input node can be improved by a decision-directed common-mode control loop, which reduces the required supply voltage.
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