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Device technology development for ul...

Nasrullah, Jawad.

Device technology development for ultra-low-power circuit design.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Device technology development for ultra-low-power circuit design.
Author:	Nasrullah, Jawad.
Description:	182 p.
Notes:	Adviser: G. Leonard Tyler.
Notes:	Source: Dissertation Abstracts International, Volume: 66-01, Section: B, page: 0456.
Contained By:	Dissertation Abstracts International66-01B.
Subject:	Engineering, Electronics and Electrical.
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3162308
ISBN:	0496960008

Device technology development for ultra-low-power circuit design.
Nasrullah, Jawad.

Device technology development for ultra-low-power circuit design. - 182 p.

Adviser: G. Leonard Tyler.

Thesis (Ph.D.)--Stanford University, 2005.

Ultra-low-power (ULP) circuit techniques incorporating dynamic threshold-voltage control through back-gate bias have promise for power control of leading-edge fine-geometry CMOS. The use of an edge-defined patterning process makes it possible to aggressively reduce the scale of thin-film transistors with back-gate-bias threshold-voltage control in a 3-D compatible IC process. With this approach, nanometer (nm) scale lines patterned in silicon, using 1-micrometer optical lithography with standard materials and standard processing equipment, are compatible with low-thermal-budget processes. For implementation, chemical-vapor deposition (CVD) defines spacers around optically-registered edges. These spacers are combined subsequently with a photoresist mask to pattern underlying layers. Ability to control variations in CVD and dry etching processes to less than 5% enables tight spacer-width control for patterning of features in the range of 18 to 180 nm. Local critical-dimension (CD) variations of up to 7 nm, based on CD-SEM analysis, are observed in test structures. Spacer-deposition roughness, oxide-etch chemistry, and edge-registration lithography contribute to CD variations and line-edge roughness. Analysis of deposited silicon and silicon-dioxide film surface roughness demonstrates that films thinner than about 20 nm are well formed when deposited more thickly than needed, and then reduced by etching to the desired dimension. Use of a binary process, consisting of alternating etching in hydrofluoric acid and nitric acid, improves roughness control. Insulated back-gated prototype thin-film transistors incorporate a 90-nm gate-length created by the use of edge-defined lithographic process. Threshold voltages of these devices are adjustable by about 100 mV per volt of back-gate bias. Intra-die variations are observed in the electrical characteristics of these devices. It is hypothesized that these variations are the result of polycrystalline-silicon grain-boundary charge traps, and channel shortening due to enhanced dopant diffusion along grain boundaries.

ISBN: 0496960008Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Device technology development for ultra-low-power circuit design.
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520 # $a Ultra-low-power (ULP) circuit techniques incorporating dynamic threshold-voltage control through back-gate bias have promise for power control of leading-edge fine-geometry CMOS. The use of an edge-defined patterning process makes it possible to aggressively reduce the scale of thin-film transistors with back-gate-bias threshold-voltage control in a 3-D compatible IC process. With this approach, nanometer (nm) scale lines patterned in silicon, using 1-micrometer optical lithography with standard materials and standard processing equipment, are compatible with low-thermal-budget processes. For implementation, chemical-vapor deposition (CVD) defines spacers around optically-registered edges. These spacers are combined subsequently with a photoresist mask to pattern underlying layers. Ability to control variations in CVD and dry etching processes to less than 5% enables tight spacer-width control for patterning of features in the range of 18 to 180 nm. Local critical-dimension (CD) variations of up to 7 nm, based on CD-SEM analysis, are observed in test structures. Spacer-deposition roughness, oxide-etch chemistry, and edge-registration lithography contribute to CD variations and line-edge roughness. Analysis of deposited silicon and silicon-dioxide film surface roughness demonstrates that films thinner than about 20 nm are well formed when deposited more thickly than needed, and then reduced by etching to the desired dimension. Use of a binary process, consisting of alternating etching in hydrofluoric acid and nitric acid, improves roughness control. Insulated back-gated prototype thin-film transistors incorporate a 90-nm gate-length created by the use of edge-defined lithographic process. Threshold voltages of these devices are adjustable by about 100 mV per volt of back-gate bias. Intra-die variations are observed in the electrical characteristics of these devices. It is hypothesized that these variations are the result of polycrystalline-silicon grain-boundary charge traps, and channel shortening due to enhanced dopant diffusion along grain boundaries.
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