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Design and analysis of reconfigurabl...

Mai, Ken.

Design and analysis of reconfigurable memories.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Design and analysis of reconfigurable memories.
Author:	Mai, Ken.
Description:	134 p.
Notes:	Adviser: Mark Horowitz.
Notes:	Source: Dissertation Abstracts International, Volume: 66-04, Section: B, page: 2236.
Contained By:	Dissertation Abstracts International66-04B.
Subject:	Engineering, Electronics and Electrical.
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3171648
ISBN:	0542083779

Design and analysis of reconfigurable memories.
Mai, Ken.

Design and analysis of reconfigurable memories. - 134 p.

Adviser: Mark Horowitz.

Thesis (Ph.D.)--Stanford University, 2005.

Decades of technology scaling have made available an unprecedented amount of computational power from today's integrated circuits. However, continued process scaling has come at the price of ever more exotic process technologies and complex designs. Due these difficulties, the non-recurring engineering cost of custom ASIC development is growing, making ASICs economically infeasible for all but the highest volume parts. However, future applications will require more efficient, high-performance computation than general purpose processors can provide. One promising approach to breaking this impasse is to use reconfigurable architectures that keep the low nonrecurring engineering costs of general purpose silicon, yet still provide efficiency and performance near that of custom ASICs. While there is a large body of work on designing reconfigurable computation, reconfigurable memory systems have been largely ignored. In this work, we examine how to add reconfigurability to the memory system.

ISBN: 0542083779Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Design and analysis of reconfigurable memories.
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245 1 0 $a Design and analysis of reconfigurable memories.
300 $a 134 p.
500 $a Adviser: Mark Horowitz.
500 $a Source: Dissertation Abstracts International, Volume: 66-04, Section: B, page: 2236.
502 $a Thesis (Ph.D.)--Stanford University, 2005.
520 # $a Decades of technology scaling have made available an unprecedented amount of computational power from today's integrated circuits. However, continued process scaling has come at the price of ever more exotic process technologies and complex designs. Due these difficulties, the non-recurring engineering cost of custom ASIC development is growing, making ASICs economically infeasible for all but the highest volume parts. However, future applications will require more efficient, high-performance computation than general purpose processors can provide. One promising approach to breaking this impasse is to use reconfigurable architectures that keep the low nonrecurring engineering costs of general purpose silicon, yet still provide efficiency and performance near that of custom ASICs. While there is a large body of work on designing reconfigurable computation, reconfigurable memory systems have been largely ignored. In this work, we examine how to add reconfigurability to the memory system.
520 # $a Looking closely at how memory is used in modern digital systems, we recognized that the most common memory structures, such as caches, FIFOs, and scratchpads, use very similar memory building blocks. By adding a few meta-data bits and a small amount of peripheral logic to a basic SRAM array, we designed a reconfigurable memory mat that could form the core of a many common memory structures. Adding a flexible interconnection network between the mats and the computation facilitates aggregation of the mats into larger, more complex memory structures.
520 # $a To evaluate our design, we implemented a prototype reconfigurable memory testchip in a 0.18mum CMOS technology. The testchip operates at 1.1GHz at the nominal 1.8V Vdd and room temperature. The prototype uses a 16kb SRAM mat and achieved area and power overheads of 32% and 23% of the totals respectively. Our projections show that the reconfiguration overheads can be reduced to below 15% of the area and below 10% of the power by using larger capacity SRAMs. The testchip shows that we can build a generic reconfigurable memory block that can form the basis of many different memory structures, while maintaining high-performance and low power.
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