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Integration of physical design and s...
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Chong, Philip.
Integration of physical design and sequential optimization.
Record Type:
Electronic resources : Monograph/item
Title/Author:
Integration of physical design and sequential optimization.
Author:
Chong, Philip.
Description:
104 p.
Notes:
Adviser: Robert K. Brayton.
Notes:
Source: Dissertation Abstracts International, Volume: 67-08, Section: B, page: 4590.
Contained By:
Dissertation Abstracts International67-08B.
Subject:
Engineering, Electronics and Electrical.
Online resource:
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3228293
ISBN:
9780542822551
Integration of physical design and sequential optimization.
Chong, Philip.
Integration of physical design and sequential optimization.
- 104 p.
Adviser: Robert K. Brayton.
Thesis (Ph.D.)--University of California, Berkeley, 2006.
This work examines the interaction between the physical design of digital integrated circuits and sequential optimization techniques used for performance enhancement. In particular, the integration of floorplanning and placement with retiming and clock skew scheduling is explored. A theoretical result is given which addresses the computational complexity of circuit partitioning under constraints derived from sequential optimization; this motivates the need for heuristic approaches to the related placement problem. Another theoretical result provides a characterization of the feasible retimings of a sequential circuit; this result is used to motivate an effective method for floorplanning integrated with sequential optimization. Practical techniques for using sequential slack to drive standard-cell placement are shown here; experiments demonstrate significant improvement in final design performance using these methods. Another part of this work examines how the role of sequential optimization and physical design changes when the design allows for asynchronous or latency-insensitive communication between modules. A theoretical result relating to the problem of clock tree implementation for clock skew scheduling under process variation is given. Finally an experimental technique for floorplanning using nonlinear programming is demonstrated.
ISBN: 9780542822551Subjects--Topical Terms:
226981
Engineering, Electronics and Electrical.
Integration of physical design and sequential optimization.
LDR
:02294nmm _2200253 _450
001
180642
005
20080111103804.5
008
090528s2006 eng d
020
$a
9780542822551
035
$a
00311667
040
$a
UMI
$c
UMI
100
0
$a
Chong, Philip.
$3
264219
245
1 0
$a
Integration of physical design and sequential optimization.
300
$a
104 p.
500
$a
Adviser: Robert K. Brayton.
500
$a
Source: Dissertation Abstracts International, Volume: 67-08, Section: B, page: 4590.
502
$a
Thesis (Ph.D.)--University of California, Berkeley, 2006.
520
#
$a
This work examines the interaction between the physical design of digital integrated circuits and sequential optimization techniques used for performance enhancement. In particular, the integration of floorplanning and placement with retiming and clock skew scheduling is explored. A theoretical result is given which addresses the computational complexity of circuit partitioning under constraints derived from sequential optimization; this motivates the need for heuristic approaches to the related placement problem. Another theoretical result provides a characterization of the feasible retimings of a sequential circuit; this result is used to motivate an effective method for floorplanning integrated with sequential optimization. Practical techniques for using sequential slack to drive standard-cell placement are shown here; experiments demonstrate significant improvement in final design performance using these methods. Another part of this work examines how the role of sequential optimization and physical design changes when the design allows for asynchronous or latency-insensitive communication between modules. A theoretical result relating to the problem of clock tree implementation for clock skew scheduling under process variation is given. Finally an experimental technique for floorplanning using nonlinear programming is demonstrated.
590
$a
School code: 0028.
650
# 0
$a
Engineering, Electronics and Electrical.
$3
226981
690
$a
0544
710
0 #
$a
University of California, Berkeley.
$3
212474
773
0 #
$g
67-08B.
$t
Dissertation Abstracts International
790
$a
0028
790
1 0
$a
Brayton, Robert K.,
$e
advisor
791
$a
Ph.D.
792
$a
2006
856
4 0
$u
http://libsw.nuk.edu.tw:81/login?url=http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3228293
$z
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3228293
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