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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation :15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings

Record Type:	Electronic resources : Monograph/item
Title/Author:	Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation :edited by Vassilis Paliouras, Johan Vounckx, Diederik Verkest.
Reminder of title:	15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings
remainder title:	PATMOS 2005
other author:	Paliouras, Vassilis.
corporate name:
Published:	Berlin Heidelberg :Springer-Verlag GmbH.,2005.
Description:	xv, 753 p. :ill., digital ;24 cm.
Series:	Lecture Notes in Computer Science,
Contained By:	Springer e-books
Subject:	Integrated circuitsCongresses.Very large scale integration
Online resource:	http://dx.doi.org/10.1007/11556930
ISBN:	9783540290131 (paper)

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation :15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation :15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings[electronic resource] /PATMOS 2005edited by Vassilis Paliouras, Johan Vounckx, Diederik Verkest. - Berlin Heidelberg :Springer-Verlag GmbH.,2005. - xv, 753 p. :ill., digital ;24 cm. - Lecture Notes in Computer Science,37280302-9743 ;.

ISBN: 9783540290131 (paper)Subjects--Topical Terms:

436461
Integrated circuits
--Very large scale integration--Congresses.

LC Class. No.: TK7874.75 / .P38 2005

Dewey Class. No.: 621.3815

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation :15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings
LDR:01106nmm _22002535a_450 001 189307
003 Springer
005 20080501093300.0
006 m d
007 cr nn 008maaau
008 090528s2005 gw j eng d
020 $a 9783540290131 (paper)
020 $a 9783540320807 (electronic bk.)
035 $a 00342358
050 0 0 $a TK7874.75 $b .P38 2005
082 0 0 $2 22 $a 621.3815
090 $a TK7874.75 $b .P311 2005
111 0 $n (3rd : $d 1998 : $c Amsterdam, Netherlands) $3 194767
245 1 0 $a Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : $b 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings $c edited by Vassilis Paliouras, Johan Vounckx, Diederik Verkest. $h [electronic resource] /
246 3 0 $a PATMOS 2005
260 # $a Berlin Heidelberg : $c 2005. $b Springer-Verlag GmbH.,
300 $a xv, 753 p. : $b ill., digital ; $c 24 cm.
440 0 $a Lecture Notes in Computer Science, $v 3728 $x 0302-9743 ;
650 # 0 $a Integrated circuits $x Very large scale integration $x Computer-aided design $v Congresses. $3 436461
650 # 0 $a Computer Science. $3 212513
650 # 0 $a Arithmetic and Logic Structures. $3 276274
650 # 0 $a Computer-Aided Engineering (CAD, CAE) and Design. $3 274500
650 # 0 $a Electronic and Computer Engineering. $3 274098
650 # 0 $a Logic Design. $3 276275
650 # 0 $a Performance and Reliability. $3 277564
650 # 0 $a Processor Architectures. $3 274498
700 0 # $a Paliouras, Vassilis. $3 285146
700 0 # $a Verkest, Diederik. $3 285147
700 0 # $a Vounckx, Johan. $3 279875
710 0 # $a SpringerLink (Online service) $3 273601
773 0 # $t Springer e-books
856 4 0 $u http://libsw.nuk.edu.tw/login?url=http://dx.doi.org/10.1007/11556930 $z http://dx.doi.org/10.1007/11556930
950 $a Computer Science (Springer-11645; ZDB-2-SCS)