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Verification by error modeling :usin...

Radecka, Katarzyna.

Verification by error modeling :using testing techniques in hardware verification

Record Type:	Electronic resources : Monograph/item
Title/Author:	Verification by error modeling :written by Katarzyna Radecka, Zeljko Zilic.
Reminder of title:	using testing techniques in hardware verification
Author:	Radecka, Katarzyna.
other author:	Zilic, Zeljko.
Published:	Boston :Springer Science + Business Media, Inc.,c2004.
Description:	xiv, 216 p. :ill., digital ;25 cm.
Series:	Frontiers in electronic testing ;
Contained By:	Springer e-books
Subject:	Integrated circuitsVery large scale integration
Online resource:	http://libsw.nuk.edu.tw:81/login?url=http://dx.doi.org/10.1007/b105974
ISBN:	9780306487392 (electronic bk.)

Verification by error modeling :using testing techniques in hardware verification
Radecka, Katarzyna.

Verification by error modeling :using testing techniques in hardware verification[electronic resource] /written by Katarzyna Radecka, Zeljko Zilic. - Boston :Springer Science + Business Media, Inc.,c2004. - xiv, 216 p. :ill., digital ;25 cm. - Frontiers in electronic testing ;25.

ISBN: 9780306487392 (electronic bk.)Subjects--Topical Terms:

184578
Integrated circuits
--Very large scale integration

LC Class. No.: TK7874.75 / .R33 2004

Dewey Class. No.: 621.395

Verification by error modeling :using testing techniques in hardware verification
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