具有IEEE 1500測試標準之三維電腦繪圖系統晶片的可測試性技術 = ...
國立高雄大學資訊工程學系碩士班

 

  • 具有IEEE 1500測試標準之三維電腦繪圖系統晶片的可測試性技術 = Design for Testability of 3D Graphics SoC with IEEE 1500 Standard
  • 紀錄類型: 書目-語言資料,印刷品 : 單行本
    並列題名: Design for Testability of 3D Graphics SoC with IEEE 1500 Standard
    作者: 蘇湘涵,
    其他團體作者: 國立高雄大學
    出版地: [高雄市]
    出版者: 撰者;
    出版年: 2010[民99]
    面頁冊數: 81面圖,表 : 30公分;
    標題: 3D繪圖系統晶片
    標題: 3D Graphics SoC
    電子資源: http://handle.ncl.edu.tw/11296/ndltd/41643836332655490504
    摘要註: 隨著生活品質提高,各種電子資訊技術發達,各種電子產品出現讓我們的生活更加方便,像是可以隨時隨地接收到最新資訊的PDA,捷運站方便簡單的購票系統,7-11門市提供各種福利的ibon,不管去到哪邊,都會有相關服務系統介面為我們解決需求。為了可以適應各種的年齡層,不管大人小孩都可以簡單的操作這些電子產品,其系統介面都是使用圖形化使用者介面(Graphical User Inter -face)的設計,利用簡單的圖示或說明來讓使用者明白其功用,並能夠依照其指示來使用介面上的功能。 而SoC(System-on-Chip)近來發展蓬勃,其相關技術如軟硬體協同設定、SoC(System-on-Chip)驗證技術、低功率消耗、IP的可重用性、與嵌入式軟體移植與開發也逐漸興起,使他原有的面積小、速度快、耗電低等等優點更加進步。 傳統的scan-based電路設計花費了很多的測試時間在測試向量的輸入上,所以測試成本提高了很多。在這篇論文裡,利用了IEEE-1500標準測試電路來針對系統進行測試,並結合BIST(Built-In Self-Testing)技術。在這樣的測試環境下,除了原本IEEE-1500標準測試電路機制所具備的功能外更進一步的使用BIST(Built-In Self-Testing)來對待測電路進行測試,並整合運用到3D繪圖系統晶片上。 As the quality of the life improves, various electronic information technologies are developed and various electronic products make our life more convenient, such as PDA which can receive the latest message any time wherever we go, the ticket purchasing system, the ibon system of 7-11 which offers the different welfare. No matter where we go, there are many relevant service system interfaces to solve the requirement of us. In order to let electronic products could be easily handled by people of any age bracket, all the system interfaces are designed to be the Graphical User Interface (GUI). The user can understand the system functions by simple icon or instruction. Following the GUI instructions, user can use the system functions. Recently, the developments of SoC techniques are popular, such as Hardware and Software Association set, SoC (System-on-Chip) check technology, low power consumption, the reuse of IP, and embedded software development and so on, so that the area can be smaller, speed of process can be faster and the power consumption can be lower, etc. Traditional IEEE-1500-based circuit needs many test time to scan input the test pattern. It raises the testing cost a lot. In this thesis, we combine the IEEE-1500 standard and Built-In Self-Testing (BIST) technique to test the system. Under such test environment, not only the functions of IEEE-1500 standard, but also the fast testing advantage of BIST (Built-In Self-Testing) can be achieved when test the circuit. We apply it to test many benchmark circuits and 3D Graphics SoC as well as.
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310001953176 博碩士論文區(二樓) 不外借資料 學位論文 TH 008M/0019 464103 4433 2010 一般使用(Normal) 在架 0
310001953184 博碩士論文區(二樓) 不外借資料 學位論文 TH 008M/0019 464103 4433 2010 c.2 一般使用(Normal) 在架 0
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