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The gm/ID Methodology, a sizing tool...

Jespers, Paul.

The gm/ID Methodology, a sizing tool for low-voltage analog CMOS circuitsthe semi-empirical and compact model approaches /

Record Type:	Electronic resources : Monograph/item
Title/Author:	The gm/ID Methodology, a sizing tool for low-voltage analog CMOS circuitsby Paul Jespers.
Reminder of title:	the semi-empirical and compact model approaches /
Author:	Jespers, Paul.
Published:	Boston, MA :Springer Science+Business Media, LLC,2010.
Description:	xvi, 171 p. :ill., digital ;24 cm.
Series:	Analog circuits and signal processing
Contained By:	Springer eBooks
Subject:	Metal oxide semiconductors, ComplementaryDesign and construction.
Online resource:	http://dx.doi.org/10.1007/978-0-387-47101-3
ISBN:	9780387471013 (electronic bk.)

The gm/ID Methodology, a sizing tool for low-voltage analog CMOS circuitsthe semi-empirical and compact model approaches /
Jespers, Paul.

The gm/ID Methodology, a sizing tool for low-voltage analog CMOS circuitsthe semi-empirical and compact model approaches /[electronic resource] :by Paul Jespers. - Boston, MA :Springer Science+Business Media, LLC,2010. - xvi, 171 p. :ill., digital ;24 cm. - Analog circuits and signal processing.

ISBN: 9780387471013 (electronic bk.)Subjects--Topical Terms:

184363
Metal oxide semiconductors, Complementary
--Design and construction.

LC Class. No.: TK7871.99.M44 / J47 2010

Dewey Class. No.: 621.3815

The gm/ID Methodology, a sizing tool for low-voltage analog CMOS circuitsthe semi-empirical and compact model approaches /
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