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針對 High-k/Metal Gate 金氧半場效電晶體在不同後製程處...

國立高雄大學電機工程學系碩士班

針對 High-k/Metal Gate 金氧半場效電晶體在不同後製程處理的分析與探討 = The Study of High-k/Metal Gate CMOSFET with Various Post Treatments

Record Type:	Language materials, printed : monographic
Paralel Title:	The Study of High-k/Metal Gate CMOSFET with Various Post Treatments
Author:	鄭濟允,
Secondary Intellectual Responsibility:	國立高雄大學
Place of Publication:	[高雄市]
Published:	撰者;
Year of Publication:	民100
Description:	86葉圖，表格 : 30公分;
Subject:	覆蓋層
Subject:	Capping layer
Online resource:	http://handle.ncl.edu.tw/11296/ndltd/23233775972857592955
Notes:	參考書目：葉81-83
Notes:	內容為英文
Summary:	在本論文的研究中，我們量測了Gate Last和Gate First的元件。對Gate Last來說，高介電值金屬閘極元件在經過熱退火製程之後，氧和氮會擴散到高介電值金屬閘極元件之中。元件的臨界電壓在PMA處理之後將會有所改變。其中摻雜氧的PMA製程最能夠改善元件的操作電流衰退、介面陷阱密度和本體缺陷等問題。　　對Gate First元件來說，不同程度的沉積會形成不同厚度的覆蓋層。這些沉積的覆蓋層可以改善漏電流的問題，但是越厚的覆蓋層會造成閘極介電層之中有更多的介面陷阱和氧空缺，進而造成更大的臨界電壓偏移。所以沉積的氧化層厚度應該要謹慎的選擇一個適當的量。　　Gate First製程在業界的發展比Gate Last製程早而且成熟，這使得Gate First製程有個好處，就是在積體電路設計和製程上不需改變太多步驟即可作業，例如32奈米和28奈米製程就是如此。但最大的關鍵在於，進入28奈米世代之後，Gate Last製程的元件電性將會比Gate First製程優良。　　In this study, there were both experimental measurements of gate last and gate first devices. For gate last ones, the oxygen and nitrogen were shown to diffuse through the TiN layer in the high-k/metal gate devices during PMA. The threshold voltages of the devices changed with various PMA conditions. The degradation of drive currents, Dit and the bulk traps of the devices were improved the most with the oxygen treatments.　　For gate first devices, the various cycles of deposition would form various thicknesses of the capping layer. The deposition of capping layer could improve the leakage problems, but thicker capping layer of the gate first devices would induce more Dit and oxygen vacancies in gate dielectric, thus causing larger threshold voltage shift. The deposition cycles of capping layer should be chosen carefully.　　Gate first process was developed into manufacturing earlier than gate last. The fact leads to one of the advantages is that the integrated circuits design would not have to be changed so much for gate first, like 32nm or 28nm process. But an important point is that the GL devices will have better characteristics than the GF ones while the fabrication process beyond 28nm technology node.

針對 High-k/Metal Gate 金氧半場效電晶體在不同後製程處理的分析與探討 = The Study of High-k/Metal Gate CMOSFET with Various Post Treatments
鄭, 濟允

針對 High-k/Metal Gate 金氧半場效電晶體在不同後製程處理的分析與探討 = The Study of High-k/Metal Gate CMOSFET with Various Post Treatments / 鄭濟允撰 - [高雄市] : 撰者, 民100. - 86葉 ; 圖，表格 ; 30公分.
參考書目：葉81-83內容為英文.
覆蓋層Capping layer

針對 High-k/Metal Gate 金氧半場效電晶體在不同後製程處理的分析與探討 = The Study of High-k/Metal Gate CMOSFET with Various Post Treatments
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328 $a 碩士論文--國立高雄大學電機工程學系碩士班
330 $a 在本論文的研究中，我們量測了Gate Last和Gate First的元件。對Gate Last來說，高介電值金屬閘極元件在經過熱退火製程之後，氧和氮會擴散到高介電值金屬閘極元件之中。元件的臨界電壓在PMA處理之後將會有所改變。其中摻雜氧的PMA製程最能夠改善元件的操作電流衰退、介面陷阱密度和本體缺陷等問題。　　對Gate First元件來說，不同程度的沉積會形成不同厚度的覆蓋層。這些沉積的覆蓋層可以改善漏電流的問題，但是越厚的覆蓋層會造成閘極介電層之中有更多的介面陷阱和氧空缺，進而造成更大的臨界電壓偏移。所以沉積的氧化層厚度應該要謹慎的選擇一個適當的量。　　Gate First製程在業界的發展比Gate Last製程早而且成熟，這使得Gate First製程有個好處，就是在積體電路設計和製程上不需改變太多步驟即可作業，例如32奈米和28奈米製程就是如此。但最大的關鍵在於，進入28奈米世代之後，Gate Last製程的元件電性將會比Gate First製程優良。　　In this study, there were both experimental measurements of gate last and gate first devices. For gate last ones, the oxygen and nitrogen were shown to diffuse through the TiN layer in the high-k/metal gate devices during PMA. The threshold voltages of the devices changed with various PMA conditions. The degradation of drive currents, Dit and the bulk traps of the devices were improved the most with the oxygen treatments.　　For gate first devices, the various cycles of deposition would form various thicknesses of the capping layer. The deposition of capping layer could improve the leakage problems, but thicker capping layer of the gate first devices would induce more Dit and oxygen vacancies in gate dielectric, thus causing larger threshold voltage shift. The deposition cycles of capping layer should be chosen carefully.　　Gate first process was developed into manufacturing earlier than gate last. The fact leads to one of the advantages is that the integrated circuits design would not have to be changed so much for gate first, like 32nm or 28nm process. But an important point is that the GL devices will have better characteristics than the GF ones while the fabrication process beyond 28nm technology node.
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