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Robust circuit & architecture design...

Ashraf, Rehman.

Robust circuit & architecture design in the nanoscale regime.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Robust circuit & architecture design in the nanoscale regime.
Author:	Ashraf, Rehman.
Description:	193 p.
Notes:	Source: Dissertation Abstracts International, Volume: 72-07, Section: B, page: .
Notes:	Adviser: Malgorzata Chrzanowska-Jeske.
Contained By:	Dissertation Abstracts International72-07B.
Subject:	Engineering, Computer.
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3453525
ISBN:	9781124616285

Robust circuit & architecture design in the nanoscale regime.
Ashraf, Rehman.

Robust circuit & architecture design in the nanoscale regime. - 193 p.

Source: Dissertation Abstracts International, Volume: 72-07, Section: B, page: .

Thesis (Ph.D.)--Portland State University, 2011.

Silicon based integrated circuit (IC) technology is approaching its physical limits. For sub 10nm technology nodes, the carbon nanotube (CNT) based field effect transistor has emerged as a promising device because of its excellent electronic properties. One of the major challenges faced by the CNT technology is the unwanted growth of metallic tubes. At present, there is no known CNT fabrication technology which allows the fabrication of 100% semiconducting CNTs. The presence of metallic tubes creates a short between the drain and source terminals of the transistor and has a detrimental impact on the delay, static power and yield of CNT based gates.

ISBN: 9781124616285Subjects--Topical Terms:

384375
Engineering, Computer.

Robust circuit & architecture design in the nanoscale regime.
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035 $a (UMI)AAI3453525
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100 1 $a Ashraf, Rehman. $3 531050
245 1 0 $a Robust circuit & architecture design in the nanoscale regime.
300 $a 193 p.
500 $a Source: Dissertation Abstracts International, Volume: 72-07, Section: B, page: .
500 $a Adviser: Malgorzata Chrzanowska-Jeske.
502 $a Thesis (Ph.D.)--Portland State University, 2011.
520 $a Silicon based integrated circuit (IC) technology is approaching its physical limits. For sub 10nm technology nodes, the carbon nanotube (CNT) based field effect transistor has emerged as a promising device because of its excellent electronic properties. One of the major challenges faced by the CNT technology is the unwanted growth of metallic tubes. At present, there is no known CNT fabrication technology which allows the fabrication of 100% semiconducting CNTs. The presence of metallic tubes creates a short between the drain and source terminals of the transistor and has a detrimental impact on the delay, static power and yield of CNT based gates.
520 $a This thesis will address the challenge of designing robust carbon nanotube based circuits in the presence of metallic tubes. For a small percentage of metallic tubes, circuit level solutions are proposed to increase the functional yield of CNT based gates in the presence of metallic tubes. Accurate analytical models with less than a 3% inaccuracy rate are developed to estimate the yield of CNT based circuit for a different percentage of metallic tubes and different drive strengths of logic gates. Moreover, a design methodology is developed for yield-aware carbon nanotube based circuits in the presence of metallic tubes using different CNFET transistor configurations. Architecture based on regular logic bricks with underlying hybrid CNFET configurations are developed which gives better trade-offs in terms of performance, power, and functional yield.
520 $a In the case when the percentage of metallic tubes is large, the proposed circuit level techniques are not sufficient. Extra processing techniques must be applied to remove the metallic tubes. The tube removal techniques have trade-offs, as the removal process is not perfect and removes semiconducting tubes in addition to removing unwanted metallic tubes. As a result, stochastic removal of tubes from the drive and fanout gate(s) results in large variation in the performance of CNFET based gates and in the worst case open circuit gates. A Monte Carlo simulation engine is developed to estimate the impact of the removal of tubes on the performance and power of CNFET based logic gates. For a quick estimation of functional yield of logic gates, accurate analytical models are developed to estimate the functional yield of logic gates when a fraction of the tubes are removed.
520 $a An efficient tube level redundancy (TLR) is proposed, resulting in a high functional yield of carbon nanotube based circuits with minimal overheads in terms of area and power when large fraction of tubes are removed. Furthermore, for applications where parallelism can be utilized we propose to increase the functional yield of the CNFET based circuits by increasing the logic depth of gates.
590 $a School code: 0180.
650 4 $a Engineering, Computer. $3 384375
650 4 $a Engineering, Electronics and Electrical. $3 226981
650 4 $a Nanotechnology. $3 193873
690 $a 0464
690 $a 0544
690 $a 0652
710 2 $a Portland State University. $b Electrical and Computer Engineering. $3 531051
773 0 $t Dissertation Abstracts International $g 72-07B.
790 1 0 $a Chrzanowska-Jeske, Malgorzata, $e advisor
790 1 0 $a Narendra, Siva $e committee member
790 1 0 $a Daasch, W. Robert $e committee member
790 1 0 $a Hall, Douglas V. $e committee member
790 1 0 $a Daim, Tugrul U. $e committee member
790 $a 0180
791 $a Ph.D.
792 $a 2011
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3453525