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Designing Digital Computer Systems w...

Ebooks Corporation.

Designing Digital Computer Systems with Verilog.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Designing Digital Computer Systems with Verilog.
Author:	Lilja, David J.
other author:	Sapatnekar, Sachin S.
Published:	Leiden :Cambridge University Press,2004.
Description:	176 p.
Subject:	Verilog (Computer hardware description language).
Online resource:	Click here to view book
ISBN:	9780511607059 (electronic bk.)

Designing Digital Computer Systems with Verilog.
Lilja, David J.

Designing Digital Computer Systems with Verilog.[electronic resource]. - Leiden :Cambridge University Press,2004. - 176 p.

Cover; Half-title; Title; Copyright; Contents; Preface; 1 Controlling complexity; 2 A Verilogical place to start; 3 Defining the instruction set architecture; 4 Algorithmic behavioral modeling; 5 Building an assembler for VeSPA; 6 Pipelining; 7 Implementation of the pipelined processor; 8 Verification; APPENDIX A The VeSPA instruction set architecture (ISA); APPENDIX B The VASM assembler; Index

This is both an introduction to computer architecture and a guide to using a hardware description language (HDL) to design a simple processor. The authors demonstrate how behavioral and structural models can be developed using the popular Verilog HDL. For senior and graduate students, and practising engineers.

Electronic reproduction.

Available via World Wide Web.

Mode of access: World Wide Web.

ISBN: 9780511607059 (electronic bk.)Subjects--Topical Terms:

246326
Verilog (Computer hardware description language).
Index Terms--Genre/Form:

214472
Electronic books.

LC Class. No.: TK7885.7 .L55 2005eb

Dewey Class. No.: 621.392

Designing Digital Computer Systems with Verilog.
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020 $a 9780511607059 (electronic bk.)
020 $a 9780521828666 (print)
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035 $a EBL283578
040 $a AU-PeEL $c AU-PeEL $d AU-PeEL
050 0 0 $a TK7885.7 .L55 2005eb
082 0 0 $a 621.392
100 1 $a Lilja, David J. $3 292917
245 1 0 $a Designing Digital Computer Systems with Verilog. $h [electronic resource].
260 $a Leiden : $b Cambridge University Press, $c 2004.
300 $a 176 p.
505 0 $a Cover; Half-title; Title; Copyright; Contents; Preface; 1 Controlling complexity; 2 A Verilogical place to start; 3 Defining the instruction set architecture; 4 Algorithmic behavioral modeling; 5 Building an assembler for VeSPA; 6 Pipelining; 7 Implementation of the pipelined processor; 8 Verification; APPENDIX A The VeSPA instruction set architecture (ISA); APPENDIX B The VASM assembler; Index
520 $a This is both an introduction to computer architecture and a guide to using a hardware description language (HDL) to design a simple processor. The authors demonstrate how behavioral and structural models can be developed using the popular Verilog HDL. For senior and graduate students, and practising engineers.
533 $a Electronic reproduction. $n Available via World Wide Web.
538 $a Mode of access: World Wide Web.
650 4 $a Verilog (Computer hardware description language). $3 246326
655 7 $a Electronic books. $2 local. $3 214472
700 1 $a Sapatnekar, Sachin S. $3 323235
710 2 $a Ebooks Corporation. $3 322111
776 1 $z 9780521828666
856 4 0 $z Click here to view book $u http://dx.doi.org/10.1017/CBO9780511607059