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具有IEEE 1500 測試標準之密碼系統晶片的可測試性技術 = Des...

國立高雄大學電機工程學系碩士班

具有IEEE 1500 測試標準之密碼系統晶片的可測試性技術 = Design for Testability ( DFT ) of Cryptographic SoC with IEEE Std. 1500

Record Type:	Language materials, printed : monographic
Paralel Title:	Design for Testability ( DFT ) of Cryptographic SoC with IEEE Std. 1500
Author:	蔡佳男,
Secondary Intellectual Responsibility:	國立高雄大學
Place of Publication:	[高雄市]
Published:	撰者;
Year of Publication:	2012[民101]
Description:	101面圖，表格 : 30公分;
Subject:	嵌入式核心測試
Subject:	Embedded Core Test
Online resource:	http://handle.ncl.edu.tw/11296/ndltd/16938192135394791157
Notes:	參考書目：面85-86
Notes:	附錄：1.Working Directory Structure；2.S-box Substitution
Summary:	本論文提出了幾個測試再利用的機制於系統晶片中，使矽智產更易於被測試。以IEEE Std. 1500 的邊界掃描架構來測試系統晶片的矽智產。而IEEE Std. 1500 的序列測試機制在測試大量測試試樣時需花費較多時間，於是將BIST 與邊界掃描架構整合於一起，來縮減測試上的時間，並於待測電路植入內部掃描鏈來增加測試覆蓋率。另一個測試機制為Avalon bus Test Interface Controller，以外部測試匯流排來控制測試機制，透過系統匯流排來對系統上的模組讀寫，讓使用者了解系統內部的行為。而整體驗證的流程以自動化驗證機制來做管理，來減少重覆測試時間上的冗長。 This thesis proposes several test reuse mechanisms in a Cryptographic SoC to let the hardware modules (IP) be easier to be tested. The IEEE Std. 1500 uses boundary scan structure to test the IP. It need to spend more time when using IEEE Std. 1500 serial testing mechanism to apply a large amount of test patterns. To reduce the test time, we integrate the BIST technique with the boundary scan structure. In addition, we insert the internal scan chains in the DUT to increase the fault coverage.Another testing mechanism in this thesis is the Avalon bus Test Interface Controller. It is controlled by the external test bus, and through the system bus to read and write the system component. It allows user to understand the behavior of the internal system. The overall verification process is managed by automatic verification mechanism, to reduce the test time.

具有IEEE 1500 測試標準之密碼系統晶片的可測試性技術 = Design for Testability ( DFT ) of Cryptographic SoC with IEEE Std. 1500
蔡, 佳男

具有IEEE 1500 測試標準之密碼系統晶片的可測試性技術 = Design for Testability ( DFT ) of Cryptographic SoC with IEEE Std. 1500 / 蔡佳男撰 - [高雄市] : 撰者, 2012[民101]. - 101面 ; 圖，表格 ; 30公分.
參考書目：面85-86附錄：1.Working Directory Structure；2.S-box Substitution.
嵌入式核心測試Embedded Core Test

具有IEEE 1500 測試標準之密碼系統晶片的可測試性技術 = Design for Testability ( DFT ) of Cryptographic SoC with IEEE Std. 1500
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300 $a 附錄：1.Working Directory Structure；2.S-box Substitution
314 $a 指導教授：洪進華博士
328 $a 碩士論文--國立高雄大學電機工程學系碩士班
330 $a 本論文提出了幾個測試再利用的機制於系統晶片中，使矽智產更易於被測試。以IEEE Std. 1500 的邊界掃描架構來測試系統晶片的矽智產。而IEEE Std. 1500 的序列測試機制在測試大量測試試樣時需花費較多時間，於是將BIST 與邊界掃描架構整合於一起，來縮減測試上的時間，並於待測電路植入內部掃描鏈來增加測試覆蓋率。另一個測試機制為Avalon bus Test Interface Controller，以外部測試匯流排來控制測試機制，透過系統匯流排來對系統上的模組讀寫，讓使用者了解系統內部的行為。而整體驗證的流程以自動化驗證機制來做管理，來減少重覆測試時間上的冗長。 This thesis proposes several test reuse mechanisms in a Cryptographic SoC to let the hardware modules (IP) be easier to be tested. The IEEE Std. 1500 uses boundary scan structure to test the IP. It need to spend more time when using IEEE Std. 1500 serial testing mechanism to apply a large amount of test patterns. To reduce the test time, we integrate the BIST technique with the boundary scan structure. In addition, we insert the internal scan chains in the DUT to increase the fault coverage.Another testing mechanism in this thesis is the Avalon bus Test Interface Controller. It is controlled by the external test bus, and through the system bus to read and write the system component. It allows user to understand the behavior of the internal system. The overall verification process is managed by automatic verification mechanism, to reduce the test time.
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