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化學氣相沉積碳化矽薄膜及其金-絕緣層-半元件研製 = Fabricati...

國立高雄大學電機工程學系碩士班

化學氣相沉積碳化矽薄膜及其金-絕緣層-半元件研製 = Fabrication of chemical vapor deposited SiC film and its metal-insulation layer-semiconductor device

Record Type:	Language materials, printed : monographic
Paralel Title:	Fabrication of chemical vapor deposited SiC film and its metal-insulation layer-semiconductor device
Author:	郭建宏,
Secondary Intellectual Responsibility:	國立高雄大學
Place of Publication:	[高雄市]
Published:	撰者;
Year of Publication:	2013[民102]
Description:	49面圖，表格 : 30公分;
Subject:	化學氣相沈積法
Subject:	chemical vapor deposition
Online resource:	http://handle.ncl.edu.tw/11296/ndltd/63679248343422530077
Notes:	參考書目：面45-46
[NT 15001349]:	化學氣相沉積碳化矽薄膜及其金絕緣層半元件研製
Summary:	本論文探討化學氣相沉積法(chemical vapor deposition)研究碳化矽(silicon carbide)薄膜的製作。化學氣相沉積法是以四氯化矽與甲烷作為矽與碳的來源，在矽基板上沉積此碳化矽薄膜，探討製程參數對表面形貌，厚度等的影響。在適當的情況下，沉積速率平均約為2.8 nm/s，隨著薄膜厚度增加，表面粗糙度下降，可低於10-20 nm。此碳化矽薄膜並配合後續製程製做金-碳化矽-矽的元件結構，分析其元件結構電性。隨著厚度增加，結構電容呈現遞減，而電導則呈現S型變化。經由電流與電導分析，本論文提出一模型以解釋此S型變化的原因。 In the thesis, the SiC films deposited on Si substrate prepared by chemical vapor deposition method were studied. The SiCl4 and CH4 sources were used as the precursors in the deposition process. Film deposition rate and morphology were studied. Under certain conditions, the deposition rate around 2.8 nm/s can be achieved. With film thickness increasing, smoother surface can be observed with surface roughness less than 10 - 20 nm。 With following device process, the Au-SiC-Si device was fabricated. The electrical properties were investigated. With the deposited film thickness increasing, the decreased capacitance and S-shaped conductance behaviors can be observed. A proposed model based on the electrical behavior was used to explain the S-shape conductance behavior.

化學氣相沉積碳化矽薄膜及其金-絕緣層-半元件研製 = Fabrication of chemical vapor deposited SiC film and its metal-insulation layer-semiconductor device
郭, 建宏

化學氣相沉積碳化矽薄膜及其金-絕緣層-半元件研製 = Fabrication of chemical vapor deposited SiC film and its metal-insulation layer-semiconductor device / 郭建宏撰 - [高雄市] : 撰者, 2013[民102]. - 49面 ; 圖，表格 ; 30公分.
參考書目：面45-46.
化學氣相沈積法chemical vapor deposition

化學氣相沉積碳化矽薄膜及其金-絕緣層-半元件研製 = Fabrication of chemical vapor deposited SiC film and its metal-insulation layer-semiconductor device
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200 1 $a 化學氣相沉積碳化矽薄膜及其金-絕緣層-半元件研製 $d Fabrication of chemical vapor deposited SiC film and its metal-insulation layer-semiconductor device $z eng $f 郭建宏撰
210 $a [高雄市] $c 撰者 $d 2013[民102]
215 0 $a 49面 $c 圖，表格 $d 30公分
300 $a 參考書目：面45-46
314 $a 指導教授：藍文厚博士
328 $a 碩士論文--國立高雄大學電機工程學系碩士班
330 $a 本論文探討化學氣相沉積法(chemical vapor deposition)研究碳化矽(silicon carbide)薄膜的製作。化學氣相沉積法是以四氯化矽與甲烷作為矽與碳的來源，在矽基板上沉積此碳化矽薄膜，探討製程參數對表面形貌，厚度等的影響。在適當的情況下，沉積速率平均約為2.8 nm/s，隨著薄膜厚度增加，表面粗糙度下降，可低於10-20 nm。此碳化矽薄膜並配合後續製程製做金-碳化矽-矽的元件結構，分析其元件結構電性。隨著厚度增加，結構電容呈現遞減，而電導則呈現S型變化。經由電流與電導分析，本論文提出一模型以解釋此S型變化的原因。 In the thesis, the SiC films deposited on Si substrate prepared by chemical vapor deposition method were studied. The SiCl4 and CH4 sources were used as the precursors in the deposition process. Film deposition rate and morphology were studied. Under certain conditions, the deposition rate around 2.8 nm/s can be achieved. With film thickness increasing, smoother surface can be observed with surface roughness less than 10 - 20 nm。 With following device process, the Au-SiC-Si device was fabricated. The electrical properties were investigated. With the deposited film thickness increasing, the decreased capacitance and S-shaped conductance behaviors can be observed. A proposed model based on the electrical behavior was used to explain the S-shape conductance behavior.
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517 1 $a 化學氣相沉積碳化矽薄膜及其金絕緣層半元件研製 $z chi
610 0 $a 化學氣相沈積法 $a 碳化矽 $a 電容 $a 電導
610 1 $a chemical vapor deposition $a SiC(Silicon Carbide) $a capacitance $a electrical conductance
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