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Overcoming Physical Design Challenges in Nanometer-Scale Integrated Circuits.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Overcoming Physical Design Challenges in Nanometer-Scale Integrated Circuits.
Author:	Wei, Yaoguang.
Description:	142 p.
Notes:	Source: Dissertation Abstracts International, Volume: 74-07(E), Section: B.
Notes:	Adviser: Sachin S. Sapatnekar.
Contained By:	Dissertation Abstracts International74-07B(E).
Subject:	Engineering, Electronics and Electrical.
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3556117
ISBN:	9781267978561

Overcoming Physical Design Challenges in Nanometer-Scale Integrated Circuits.
Wei, Yaoguang.

Overcoming Physical Design Challenges in Nanometer-Scale Integrated Circuits. - 142 p.

Source: Dissertation Abstracts International, Volume: 74-07(E), Section: B.

Thesis (Ph.D.)--University of Minnesota, 2013.

Through aggressive technology scaling over the past five decades, integrated circuit design has entered the nanometer-scale era. While scaling enables the design of more powerful chips, circuit designers must face numerous challenges that accompany these miniscule feature sizes. Many of these issues are expressed in the step of physical design, an important back-end stage in the integrated circuit design flow.

ISBN: 9781267978561Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Overcoming Physical Design Challenges in Nanometer-Scale Integrated Circuits.
LDR:05366nmm a2200325 4500 001 419249
005 20140520124005.5
008 140717s2013 ||||||||||||||||| ||eng d
020 $a 9781267978561
035 $a (MiAaPQ)AAI3556117
035 $a AAI3556117
040 $a MiAaPQ $c MiAaPQ
100 1 $a Wei, Yaoguang. $3 660258
245 1 0 $a Overcoming Physical Design Challenges in Nanometer-Scale Integrated Circuits.
300 $a 142 p.
500 $a Source: Dissertation Abstracts International, Volume: 74-07(E), Section: B.
500 $a Adviser: Sachin S. Sapatnekar.
502 $a Thesis (Ph.D.)--University of Minnesota, 2013.
520 $a Through aggressive technology scaling over the past five decades, integrated circuit design has entered the nanometer-scale era. While scaling enables the design of more powerful chips, circuit designers must face numerous challenges that accompany these miniscule feature sizes. Many of these issues are expressed in the step of physical design, an important back-end stage in the integrated circuit design flow.
520 $a To achieve effective routability evaluation, we first analyze the problems associated with mainstream global-routing-based congestion analysis tools. Two major deficiencies of existing approaches are: (i) they do not adequately model local routing resources, which can cause incorrect routability predictions that are only detected late, during detailed routing, (ii) the metrics used to represent congestion may yield numbers that do not provide sufficient intuition to the designer; moreover, they may often fail to predict the routability accurately. We propose solutions for both problems. First, we develop an efficient, accurate and scalable local routing resource model. Experiments demonstrate that our model improves the accuracy of a congestion analyzer and enables designers to use a coarser grid to speed up congestion analysis and achieve similar accuracy as the baseline case. Second, we develop a new metric that represents the congestion map for the chip with high fidelity. Experiments show that compared with conventional metrics, the new metric can predict the routability more accurately and can drive a placer to obtain a design that has better routability characteristics.
520 $a To reduce the buffer usage, we make full use of the timing benefits brought by the thick metal layers. In advanced technologies, a larger number of metal layers with thick cross-sections are available for routing. These metal layers have much smaller wire delays than thinner layers, and assigning nets to these layers can improve timing and save buffer usage. However, existing algorithms have various limitations in using thick metal layers. In this work, we propose a novel algorithm to address the issue. Our algorithm tries to assign as many nets as possible to thick metal layers to maximize the timing benefits while simultaneously using heuristics to control the congestion at a manageable level. We also present a new physical synthesis flow that adds our algorithm as a new component at an early stage of an existing industrial design flow. Experimental results demonstrate the effectiveness of our algorithm and flow on a set of industrial designs.
520 $a To overcome the challenges from process variations, this thesis presents physical design solutions to two important types of variations induced in the processes of oxide chemical mechanical polishing (CMP) and rapid thermal annealing (RTA). First, since the oxide CMP variation highly depends on the metal pattern density, a common practice to reduce CMP variation is to insert dummy fills. However, dummy fills have side effects on design performance or complexity and should be minimized. Therefore, we propose a novel global routing algorithm directly aiming to minimize the amount of dummy fills necessary to satisfy the requirements for CMP. Since it is not computationally efficient to directly minimize the amount of dummy fills in the routing process, we develop a surrogate optimization objective through theoretical analyses and experiments. Then effective cost functions are elaborated and applied in the routing process to optimize the surrogate metric. Our strategy and algorithm is validated by the experiments on a standard set of benchmark circuits. Second, since RTA variation strongly depends on the density of the STI regions, to minimize RTA variation, this thesis proposes a two-step approach to maximize the uniformity of the STI density throughout the layout. We introduce a concept of effective STI density and propose an efficient incremental method to compute it for the whole circuit. Furthermore, we enhance a conventional floorplanner to handle the new objective of minimizing the variations in effective STI density, using a two-stage simulated annealing heuristic. As the second step of our efforts, we insert dummy polysilicon fills to further minimize the variation in effective STI density. Experimental results demonstrate that our methods can significantly reduce the RTA variations. (Abstract shortened by UMI.).
590 $a School code: 0130.
650 4 $a Engineering, Electronics and Electrical. $3 226981
650 4 $a Engineering, Computer. $3 384375
650 4 $a Engineering, General. $3 660165
690 $a 0544
690 $a 0464
690 $a 0537
710 2 $a University of Minnesota. $b Electrical/Computer Engineering. $3 660259
773 0 $t Dissertation Abstracts International $g 74-07B(E).
790 $a 0130
791 $a Ph.D.
792 $a 2013
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3556117