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Design of Millimeter-Wave Power Amplifiers in Silicon.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Design of Millimeter-Wave Power Amplifiers in Silicon.
作者:	Kalantari, Nader.
面頁冊數:	124 p.
附註:	Source: Dissertation Abstracts International, Volume: 74-07(E), Section: B.
附註:	Adviser: James F. Buckwalter.
Contained By:	Dissertation Abstracts International74-07B(E).
標題:	Engineering, Electronics and Electrical.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3556538
ISBN:	9781267986580

Design of Millimeter-Wave Power Amplifiers in Silicon.
Kalantari, Nader.

Design of Millimeter-Wave Power Amplifiers in Silicon. - 124 p.

Source: Dissertation Abstracts International, Volume: 74-07(E), Section: B.

Thesis (Ph.D.)--University of California, San Diego, 2013.

The first part of this dissertation focuses on the millimeter-wave power amplifier in silicon where both switching and linear power amplifiers were investigated. In Chapter 2, a Q-band, Class-E power amplifier has been designed and fabricated in a 120 nm SiGe BiCMOS technology. The amplifier was designed for high output power using on-chip power combining networks. It operates respectively from a 1.2 V supply for peak efficiency and a 2.4 V supply for maximum power and occupies an area of 0.801 mm2. A peak PAE of 18% is measured for an output power of 11.3 dBm at 45 GHz and a maximum of 19.4 dBm is measured at 42 GHz with a PAE of 14.4%. The power amplifier operates from 42 to 50 GHz. Chapter 3, presents a W-band, tapered constructive wave power amplifier (TCWPA) that has been designed and fabricated in a 120 nm SiGe BiCMOS technology. The amplifier has a 3 dB BW of 19 GHz from 91-110 GHz and a maximum gain of 12.5 dB at 101 GHz. At 98 GHz, OP1dB is 4.9 dBm. At 97 GHz, saturated output power is 5.9 dBm and the PAE is 7.2%. The amplifier operates from a 2.4 V supply and occupies an area of 0.22 mm2. A novel circuit topology for power amplifier was introduced in Chapter 4 where only one network is used to provide both input and output matching. This new topology incorporates a feedback network around the transistor to satisfy matching requirements. Circuit parameters can be tuned for small- and large-signal circuit operation. The power amplifier is fabricated in a 120 nm SiGe BiCMOS process and performs from 36 to 41 GHz. The PA achieves a saturated output power of 23 dBm and a peak power added efficiency of 20% at 38 GHz.

ISBN: 9781267986580Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Design of Millimeter-Wave Power Amplifiers in Silicon.
LDR:03584nmm a2200277 4500 001 419251
005 20140520124005.5
008 140717s2013 ||||||||||||||||| ||eng d
020 $a 9781267986580
035 $a (MiAaPQ)AAI3556538
035 $a AAI3556538
040 $a MiAaPQ $c MiAaPQ
100 1 $a Kalantari, Nader. $3 660262
245 1 0 $a Design of Millimeter-Wave Power Amplifiers in Silicon.
300 $a 124 p.
500 $a Source: Dissertation Abstracts International, Volume: 74-07(E), Section: B.
500 $a Adviser: James F. Buckwalter.
502 $a Thesis (Ph.D.)--University of California, San Diego, 2013.
520 $a The first part of this dissertation focuses on the millimeter-wave power amplifier in silicon where both switching and linear power amplifiers were investigated. In Chapter 2, a Q-band, Class-E power amplifier has been designed and fabricated in a 120 nm SiGe BiCMOS technology. The amplifier was designed for high output power using on-chip power combining networks. It operates respectively from a 1.2 V supply for peak efficiency and a 2.4 V supply for maximum power and occupies an area of 0.801 mm2. A peak PAE of 18% is measured for an output power of 11.3 dBm at 45 GHz and a maximum of 19.4 dBm is measured at 42 GHz with a PAE of 14.4%. The power amplifier operates from 42 to 50 GHz. Chapter 3, presents a W-band, tapered constructive wave power amplifier (TCWPA) that has been designed and fabricated in a 120 nm SiGe BiCMOS technology. The amplifier has a 3 dB BW of 19 GHz from 91-110 GHz and a maximum gain of 12.5 dB at 101 GHz. At 98 GHz, OP1dB is 4.9 dBm. At 97 GHz, saturated output power is 5.9 dBm and the PAE is 7.2%. The amplifier operates from a 2.4 V supply and occupies an area of 0.22 mm2. A novel circuit topology for power amplifier was introduced in Chapter 4 where only one network is used to provide both input and output matching. This new topology incorporates a feedback network around the transistor to satisfy matching requirements. Circuit parameters can be tuned for small- and large-signal circuit operation. The power amplifier is fabricated in a 120 nm SiGe BiCMOS process and performs from 36 to 41 GHz. The PA achieves a saturated output power of 23 dBm and a peak power added efficiency of 20% at 38 GHz.
520 $a The second part of this dissertation focuses on the performance analysis of phase-interpolated dual loop clock and data recovery. It presents a four channel receiver for high-speed signal conditioning. Each channel consists of a continuous time linear equalizer (CTLE) and a dual loop CDR with phase-interpolator. All channels share a single PLL that generates and distributes quadrature clock phases to each CDR for data recovery. Clock amplitude, phase INL and phase DNL are derived for IQ phase error and predict phase-dependent jitter contributions to the recovered clock. The multilane receiver was designed in 130 nm CMOS technology. The die occupies an area of 1930 mum by 1250 mum and consumes 67.9 mW per channel. It achieves a maximum data rate of 7 Gbps per channel for 0 and 200 ppm clock frequency deviation. Quadrature clocks are used in locking mechanism of phase-interpolated CDRs. Due to circuit non-idealities, any mismatch in the quadrature phase causes jitter increase and ultimately increase of bit error rate. The material is presented in Chapter 5.
590 $a School code: 0033.
650 4 $a Engineering, Electronics and Electrical. $3 226981
690 $a 0544
710 2 $a University of California, San Diego. $b Electrical Engineering (Electronic Circuits and Systems). $3 660263
773 0 $t Dissertation Abstracts International $g 74-07B(E).
790 $a 0033
791 $a Ph.D.
792 $a 2013
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3556538