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Designing 2D and 3D network-on-chip ...

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Designing 2D and 3D network-on-chip architectures

Record Type:	Electronic resources : Monograph/item
Title/Author:	Designing 2D and 3D network-on-chip architecturesby Konstantinos Tatas ... [et al.].
other author:	Tatas, Konstantinos.
Published:	New York, NY :Springer New York :2014.
Description:	xiii, 265 p. :ill. (some col.), digital ;24 cm.
Contained By:	Springer eBooks
Subject:	Networks on a chipDesign.
Online resource:	http://dx.doi.org/10.1007/978-1-4614-4274-5
ISBN:	9781461442745 (electronic bk.)

Designing 2D and 3D network-on-chip architectures
Designing 2D and 3D network-on-chip architectures[electronic resource] /by Konstantinos Tatas ... [et al.]. - New York, NY :Springer New York :2014. - xiii, 265 p. :ill. (some col.), digital ;24 cm.

ISBN: 9781461442745 (electronic bk.)Subjects--Topical Terms:

674842
Networks on a chip
--Design.

Dewey Class. No.: 006.22

Designing 2D and 3D network-on-chip architectures
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245 0 0 $a Designing 2D and 3D network-on-chip architectures $h [electronic resource] / $c by Konstantinos Tatas ... [et al.].
260 $a New York, NY : $b Springer New York : $b Imprint: Springer, $c 2014.
300 $a xiii, 265 p. : $b ill. (some col.), digital ; $c 24 cm.
650 0 $a Networks on a chip $x Design. $3 674842
650 1 4 $a Engineering. $3 210888
650 2 4 $a Circuits and Systems. $3 274416
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 274412
650 2 4 $a Processor Architectures. $3 274498
700 1 $a Tatas, Konstantinos. $3 676012
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950 $a Engineering (Springer-11647)

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EB TK5105546 D457 2014

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http://dx.doi.org/10.1007/978-1-4614-4274-5

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