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A pipelined multi-core MIPS machineh...

Kovalev, Mikhail.

A pipelined multi-core MIPS machinehardware implementation and correctness proof /

Record Type:	Electronic resources : Monograph/item
Title/Author:	A pipelined multi-core MIPS machineby Mikhail Kovalev, Silvia M. Muller, Wolfgang J. Paul.
Reminder of title:	hardware implementation and correctness proof /
other author:	Kovalev, Mikhail.
Published:	Cham :Springer International Publishing :2014.
Description:	xii, 352 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
Subject:	MIPS (Computer architecture)
Online resource:	http://dx.doi.org/10.1007/978-3-319-13906-7
ISBN:	9783319139067 (electronic bk.)

A pipelined multi-core MIPS machinehardware implementation and correctness proof /
A pipelined multi-core MIPS machinehardware implementation and correctness proof /[electronic resource] :by Mikhail Kovalev, Silvia M. Muller, Wolfgang J. Paul. - Cham :Springer International Publishing :2014. - xii, 352 p. :ill., digital ;24 cm. - Lecture notes in computer science,90000302-9743 ;. - Lecture notes in computer science ;4891..

ISBN: 9783319139067 (electronic bk.)Subjects--Topical Terms:

340989
MIPS (Computer architecture)

LC Class. No.: QA76.9.A73 / P57 2014

Dewey Class. No.: 004.22

A pipelined multi-core MIPS machinehardware implementation and correctness proof /
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