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封裝產品於ESD/EOS破壞後之失效分析 = Failure Analy...

國立高雄大學電機工程學系--先進電子構裝技術產業研發碩士專班

封裝產品於ESD/EOS破壞後之失效分析 = Failure Analysis on Packaged IC with ESD/EOS Damage

Record Type:	Language materials, printed : monographic
Paralel Title:	Failure Analysis on Packaged IC with ESD/EOS Damage
Author:	盧天富,
Secondary Intellectual Responsibility:	國立高雄大學
Place of Publication:	[高雄市]
Published:	撰者;
Year of Publication:	2015[民104]
Description:	86面圖，表 : 30公分;
Subject:	失效分析
Subject:	Failure Analysis
Online resource:	http://handle.ncl.edu.tw/11296/ndltd/31147332847886955509
Notes:	104年10月31日公開
Notes:	參考書目：面86
Summary:	本論文旨在研究封裝產品,於封裝廠生產過程中所造成的靜電放電(ESD)及過度電性應力(EOS)損壞,靜電放電又分為人體放電模式(HBM)、機器放電模式(MM)、元件充電模式(CDM),利用開短路測試,光學顯微鏡極掃描式電子顯微鏡(SEM)分析,逐層檢視各層結構異常的特徵,異常的區域能有效的確認與區分,以建立一個封裝廠靜電放電與過度電性應力失效分析參考資料庫,以利後續封裝廠對於靜電放電與過度電性應力的權責區分。 This thesis aims the failure analysis due to electrostatic discharge (ESD) and electrical overstress (EOS) damage on IC packaging process. The ESD damage, including human body mode, machine mode, component charging mode and EOS damage were applied to packaged IC, respectively. The open short test and optical microscope analysis were applied layer by layer in structure for characterizing the damaged region with the scanning electron microscope(SEM) analysis, the damage region can be well identified. Specified postion, damaged area and surface morphology can be extinguished with ESD and EOS damage. With these established data base, the failure behavior in IC package process can be identified well.

封裝產品於ESD/EOS破壞後之失效分析 = Failure Analysis on Packaged IC with ESD/EOS Damage
盧, 天富

封裝產品於ESD/EOS破壞後之失效分析 = Failure Analysis on Packaged IC with ESD/EOS Damage / 盧天富撰 - [高雄市] : 撰者, 2015[民104]. - 86面 ; 圖，表 ; 30公分.
104年10月31日公開參考書目：面86.
失效分析Failure Analysis

封裝產品於ESD/EOS破壞後之失效分析 = Failure Analysis on Packaged IC with ESD/EOS Damage
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330 $a 本論文旨在研究封裝產品,於封裝廠生產過程中所造成的靜電放電(ESD)及過度電性應力(EOS)損壞,靜電放電又分為人體放電模式(HBM)、機器放電模式(MM)、元件充電模式(CDM),利用開短路測試,光學顯微鏡極掃描式電子顯微鏡(SEM)分析,逐層檢視各層結構異常的特徵,異常的區域能有效的確認與區分,以建立一個封裝廠靜電放電與過度電性應力失效分析參考資料庫,以利後續封裝廠對於靜電放電與過度電性應力的權責區分。 This thesis aims the failure analysis due to electrostatic discharge (ESD) and electrical overstress (EOS) damage on IC packaging process. The ESD damage, including human body mode, machine mode, component charging mode and EOS damage were applied to packaged IC, respectively. The open short test and optical microscope analysis were applied layer by layer in structure for characterizing the damaged region with the scanning electron microscope(SEM) analysis, the damage region can be well identified. Specified postion, damaged area and surface morphology can be extinguished with ESD and EOS damage. With these established data base, the failure behavior in IC package process can be identified well.
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