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銅線製程對銲墊受損銲線參數研究 = Study of CUP Wafer...

國立高雄大學電機工程學系--先進電子構裝技術產業研發碩士專班

銅線製程對銲墊受損銲線參數研究 = Study of CUP Wafer Pad Crack in Copper Wire Bond Process

Record Type:	Language materials, printed : monographic
Paralel Title:	Study of CUP Wafer Pad Crack in Copper Wire Bond Process
Author:	桑希強,
Secondary Intellectual Responsibility:	國立高雄大學
Place of Publication:	[高雄市]
Published:	撰者;
Year of Publication:	2015[民104]
Description:	74面圖，表 : 30公分;
Subject:	墊下線路
Subject:	circuit under pad (CUP)
Online resource:	http://handle.ncl.edu.tw/11296/ndltd/99729915028700709424
Notes:	104年10月31日公開
Notes:	參考書目：面63
Summary:	現在電子產品為講求輕、薄、短小,需要不斷的縮小晶片的體積,所以晶圓製造商必須將原來並非佈植在銲墊下方的線路,改佈植在銲墊的下方,以達成縮小晶片體積目的,此種銲墊下線路(Circuit Under Pad,CUP)的結構,在硬度高的銅線封裝打線接合過程中,可能產生銲墊受損(Pad Crack)而造成良率損失。本論文針對CUP元件,研究銅線封裝生產所造成之銲線製程缺點,研究銅線銲線製程中的參數,及晶圓的銲墊下特徵結構差異,尋找良好的銲線參數區間,並利用JMP/DOE工程手法作驗證分析,進行相關的的可靠度驗證,改善CUP元件在銲線站之銲墊受損缺點,提升封裝良率。 For developing compact electronic products, circuit under pad (CUP) structure was developed in wafer level, in the high hardness copper (Cu) wire bonding process, this CUP structure may suffer the impact and cause yield loss.This thesis study the process window in copper wire bonding process with different characteristic CUP element. Process parameters designed by JMP/DOE methods were applied in this study. With the analysis, optimized process parameters can be achieved. The final reliability verification was applied to study the yield improvement.

銅線製程對銲墊受損銲線參數研究 = Study of CUP Wafer Pad Crack in Copper Wire Bond Process
桑, 希強

銅線製程對銲墊受損銲線參數研究 = Study of CUP Wafer Pad Crack in Copper Wire Bond Process / 桑希強撰 - [高雄市] : 撰者, 2015[民104]. - 74面 ; 圖，表 ; 30公分.
104年10月31日公開參考書目：面63.
墊下線路circuit under pad (CUP)

銅線製程對銲墊受損銲線參數研究 = Study of CUP Wafer Pad Crack in Copper Wire Bond Process
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330 $a 現在電子產品為講求輕、薄、短小,需要不斷的縮小晶片的體積,所以晶圓製造商必須將原來並非佈植在銲墊下方的線路,改佈植在銲墊的下方,以達成縮小晶片體積目的,此種銲墊下線路(Circuit Under Pad,CUP)的結構,在硬度高的銅線封裝打線接合過程中,可能產生銲墊受損(Pad Crack)而造成良率損失。本論文針對CUP元件,研究銅線封裝生產所造成之銲線製程缺點,研究銅線銲線製程中的參數,及晶圓的銲墊下特徵結構差異,尋找良好的銲線參數區間,並利用JMP/DOE工程手法作驗證分析,進行相關的的可靠度驗證,改善CUP元件在銲線站之銲墊受損缺點,提升封裝良率。 For developing compact electronic products, circuit under pad (CUP) structure was developed in wafer level, in the high hardness copper (Cu) wire bonding process, this CUP structure may suffer the impact and cause yield loss.This thesis study the process window in copper wire bonding process with different characteristic CUP element. Process parameters designed by JMP/DOE methods were applied in this study. With the analysis, optimized process parameters can be achieved. The final reliability verification was applied to study the yield improvement.
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