國立高雄大學圖資館 |

Language: English

Back

Microarchitecture of network-on-chip...

Dimitrakopoulos, Giorgos.

Microarchitecture of network-on-chip routersa designer's perspective /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Microarchitecture of network-on-chip routersby Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis.
Reminder of title:	a designer's perspective /
Author:	Dimitrakopoulos, Giorgos.
other author:	Psarras, Anastasios.
Published:	New York, NY :Springer New York :2015.
Description:	xiv, 175 p. :ill. (some col.), digital ;24 cm.
Contained By:	Springer eBooks
Subject:	Networks on a chip.
Online resource:	http://dx.doi.org/10.1007/978-1-4614-4301-8
ISBN:	9781461443018 (electronic bk.)

Microarchitecture of network-on-chip routersa designer's perspective /
Dimitrakopoulos, Giorgos.

Microarchitecture of network-on-chip routersa designer's perspective /[electronic resource] :by Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis. - New York, NY :Springer New York :2015. - xiv, 175 p. :ill. (some col.), digital ;24 cm.

Introduction to network-on-chip design -- Link-level flow control and buffering -- Baseline switching modules and routers -- Arbitration logic -- Pipelined wormhole routers -- Virtual-channel flow control and buffering -- Baseline virtual-channel based switching modules and routers -- High-speed allocators for VC-based routers -- Pipelined virtual-channel-based routers.

This book provides a unified overview of network-on-chip router micro-architecture, the corresponding design opportunities and challenges, and existing solutions to overcome these challenges. The discussion focuses on the heart of a NoC, the NoC router, and how it interacts with the rest of the system. Coverage includes both basic and advanced design techniques that cover the entire router design space including router organization, flow control, pipelined operation, buffering architectures, as well as allocators' structure and algorithms. Router micro-architectural options are presented in a step-by-step manner beginning from the basic design principles. Even highly sophisticated design alternatives are categorized and broken down to simpler pieces that can be understood easily and analyzed. This book is an invaluable reference for system, architecture, circuit, and EDA researchers and developers, who are interested in understanding the overall picture of NoC routers' architecture, the associated design challenges, and the available solutions. Designed pedagogically, explaining basic functionality of each NoC router and design block, relating it to the role it plays in the system; Performance-enhancing features are added in a step-by-step manner; Justifies and explains every design choice, including the less attractive options; Includes detailed examples presenting the flow of information inside the router on a cycle-by-cycle basis, highlighting the operation of each part under regular or worst-case traffic scenarios.

ISBN: 9781461443018 (electronic bk.)

Standard No.: 10.1007/978-1-4614-4301-8doiSubjects--Topical Terms:

349077
Networks on a chip.

LC Class. No.: TK5105.546

Dewey Class. No.: 621.381531

Microarchitecture of network-on-chip routersa designer's perspective /
LDR:02932nmm a2200313 a 4500 001 459602
003 DE-He213
005 20150520154422.0
006 m d
007 cr nn 008maaau
008 151110s2015 nyu s 0 eng d
020 $a 9781461443018 (electronic bk.)
020 $a 9781461443001 (paper)
024 7 $a 10.1007/978-1-4614-4301-8 $2 doi
035 $a 978-1-4614-4301-8
040 $a GP $c GP
041 0 $a eng
050 4 $a TK5105.546
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 621.381531 $2 23
090 $a TK5105.546 $b .D582 2015
100 1 $a Dimitrakopoulos, Giorgos. $3 710453
245 1 0 $a Microarchitecture of network-on-chip routers $h [electronic resource] : $b a designer's perspective / $c by Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis.
260 $a New York, NY : $b Springer New York : $b Imprint: Springer, $c 2015.
300 $a xiv, 175 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a Introduction to network-on-chip design -- Link-level flow control and buffering -- Baseline switching modules and routers -- Arbitration logic -- Pipelined wormhole routers -- Virtual-channel flow control and buffering -- Baseline virtual-channel based switching modules and routers -- High-speed allocators for VC-based routers -- Pipelined virtual-channel-based routers.
520 $a This book provides a unified overview of network-on-chip router micro-architecture, the corresponding design opportunities and challenges, and existing solutions to overcome these challenges. The discussion focuses on the heart of a NoC, the NoC router, and how it interacts with the rest of the system. Coverage includes both basic and advanced design techniques that cover the entire router design space including router organization, flow control, pipelined operation, buffering architectures, as well as allocators' structure and algorithms. Router micro-architectural options are presented in a step-by-step manner beginning from the basic design principles. Even highly sophisticated design alternatives are categorized and broken down to simpler pieces that can be understood easily and analyzed. This book is an invaluable reference for system, architecture, circuit, and EDA researchers and developers, who are interested in understanding the overall picture of NoC routers' architecture, the associated design challenges, and the available solutions. Designed pedagogically, explaining basic functionality of each NoC router and design block, relating it to the role it plays in the system; Performance-enhancing features are added in a step-by-step manner; Justifies and explains every design choice, including the less attractive options; Includes detailed examples presenting the flow of information inside the router on a cycle-by-cycle basis, highlighting the operation of each part under regular or worst-case traffic scenarios.
650 0 $a Networks on a chip. $3 349077
650 0 $a Computer architecture. $3 183006
650 1 4 $a Engineering. $3 210888
650 2 4 $a Circuits and Systems. $3 274416
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 274412
650 2 4 $a Processor Architectures. $3 274498
700 1 $a Psarras, Anastasios. $3 710454
700 1 $a Seitanidis, Ioannis. $3 710455
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-1-4614-4301-8
950 $a Engineering (Springer-11647)