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Low-noise low-power design for phase...

Dai, Fa Foster.

Low-noise low-power design for phase-locked loopsmulti-phase high-performance oscillators /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Low-noise low-power design for phase-locked loopsby Feng Zhao, Fa Foster Dai.
其他題名:	multi-phase high-performance oscillators /
作者:	Zhao, Feng.
其他作者:	Dai, Fa Foster.
出版者:	Cham :Springer International Publishing :2015.
面頁冊數:	xiii, 96 p. :ill. (some col.), digital ;24 cm.
Contained By:	Springer eBooks
標題:	Phase-locked loops.
電子資源:	http://dx.doi.org/10.1007/978-3-319-12200-7
ISBN:	9783319122007 (electronic bk.)

Low-noise low-power design for phase-locked loopsmulti-phase high-performance oscillators /
Zhao, Feng.

Low-noise low-power design for phase-locked loopsmulti-phase high-performance oscillators /[electronic resource] :by Feng Zhao, Fa Foster Dai. - Cham :Springer International Publishing :2015. - xiii, 96 p. :ill. (some col.), digital ;24 cm.

Introduction -- Analysis of Quantization Noise Reduction Techniques for Fractional-N PLL -- A Wide-Band 0.13um SiGe BiCMOS PLL for X-Band Radar -- Design and Analysis of QVCO with Different Coupling Techniques -- Design and Analysis of a 0.6V QVCO with Capacitive-Coupling Technique -- Conclusions.

This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.

ISBN: 9783319122007 (electronic bk.)

Standard No.: 10.1007/978-3-319-12200-7doiSubjects--Topical Terms:

182354
Phase-locked loops.

LC Class. No.: TK7872.P38

Dewey Class. No.: 621.3815364

Low-noise low-power design for phase-locked loopsmulti-phase high-performance oscillators /
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300 $a xiii, 96 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a Introduction -- Analysis of Quantization Noise Reduction Techniques for Fractional-N PLL -- A Wide-Band 0.13um SiGe BiCMOS PLL for X-Band Radar -- Design and Analysis of QVCO with Different Coupling Techniques -- Design and Analysis of a 0.6V QVCO with Capacitive-Coupling Technique -- Conclusions.
520 $a This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.
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