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Design and modeling for 3D ICs and i...

Han, Ki Jin.

Design and modeling for 3D ICs and interposers

Record Type:	Electronic resources : Monograph/item
Title/Author:	Design and modeling for 3D ICs and interposersby Madhavan Swaminathan, Ki Jin Han.
Author:	Swaminathan, Madhavan.
other author:	Han, Ki Jin.
Published:	Hackensack, NJ :World Scientific2014.
Description:	1 online resource (200 p.)
Subject:	Three-dimensional integrated circuits.
Online resource:	http://www.worldscientific.com/worldscibooks/10.1142/8814#t=toc
ISBN:	9789814508605 (electronic bk.)

Design and modeling for 3D ICs and interposers
Swaminathan, Madhavan.

Design and modeling for 3D ICs and interposers[electronic resource] /by Madhavan Swaminathan, Ki Jin Han. - Hackensack, NJ :World Scientific2014. - 1 online resource (200 p.) - WSPC series in advanced integration and packaging ;2. - WSPC series in advanced integration and packaging ;v. 1..

Ch. 1. System integration and modeling concepts. 1.1. Moore's law. 1.2. IC integration vs system integration -- what is the difference? 1.3. History of integration -- an overview. 1.4. Primary drivers for 3D integration. 1.5. Role of the interposer in 3D integration. 1.6. Modeling and simulation. 1.7. Summary -- ch. 2. Modeling of cylindrical interconnections. 2.1. Introduction. 2.2. Specialized basis functions. 2.3. Electric field integral equation (EFIE) with cylindrical CMBF for resistance and inductance extraction. 2.4. Scalar potential integral equation (SPIE) with cylindrical AMBF for conductance and capacitance extraction. 2.5. Broadband equivalent RLC network. 2.6. Inclusion of planar structures. 2.7. Examples with bonding wires. 2.8. Examples with vias. 2.9. Example of package on package. 2.10. Summary -- ch. 3. Electrical modeling of through silicon vias. 3.1. Benefits of through silicon vias. 3.2. Challenges in modeling through silicon vias. 3.3. Propagating modes in through silicon vias -- an electromagnetic perspective. 3.4. Physics based modeling of through silicon vias. 3.5. Rigorous electromagnetic modeling. 3.6. Modeling of conical through silicon via. 3.7. MOS capacitance effect. 3.8. Consideration of MOS capacitance effect in electromagnetic modeling. 3.9. Time domain response. 3.10. Summary -- ch. 4. Electrical performance and signal integrity. 4.1. Process optimization. 4.2. Cross talk in interposers. 4.3. Via arrays. 4.4. Interposers. 4.5. Modeling and design challenges. 4.6. Summary -- ch. 5. Power distribution, return path discontinuities and thermal management. 5.1. Power distribution -- an overview. 5.2. Power distribution for 3D integration. 5.3. Current paths in IC and package. 5.4. Signal and power integrity -- does one affect the other? 5.5. Challenges for addressing power distribution in 3D ICs and interposers. 5.6. Thermal management and its effect on power distribution. 5.7. Summary -- ch. 6. Alternate methods for power distribution. 6.1. Introducing power transmission lines. 6.2. Constant current power transmission line (CCPTL). 6.3. Pseudo balanced power transmission line (PBPTL). 6.4. Constant voltage power transmission line (CVPTL). 6.5. Power calculations. 6.6. Application of power transmission lines to FPGA. 6.7. Managing signal and power integrity for 3D ICs. 6.8. Summary.

3D Integration is being touted as the next semiconductor revolution. This book provides a comprehensive coverage on the design and modeling aspects of 3D integration, in particularly, focus on its electrical behavior. Looking from the perspective the silicon via (TSV) and glass via (TGV) technology, the book introduces 3D ICs and Interposers as a technology, and presents its application in numerical modeling, signal integrity, power integrity and thermal integrity. The authors underscored the potential of this technology in design exchange formats and power distribution.

ISBN: 9789814508605 (electronic bk.)Subjects--Topical Terms:

717043
Three-dimensional integrated circuits.

LC Class. No.: TK7874.893

Dewey Class. No.: 621.4 / 23

Design and modeling for 3D ICs and interposers
LDR:03879cmm a2200289Ka 4500 001 463745
003 OCoLC
005 20151106095607.0
006 m o d
007 cr cnu---unuuu
008 151126s2014 nju o 000 0 eng d
020 $a 9789814508605 (electronic bk.)
020 $a 9814508608 (electronic bk.)
020 $z 9814508594
020 $z 9789814508599
035 $a (OCoLC)868319143
035 $a ocn868319143
040 $a N $b eng $c N $d STF $d OCLCO $d OCLCF
050 4 $a TK7874.893
082 0 4 $a 621.4 $b 23 $2 22
100 1 $a Swaminathan, Madhavan. $3 306904
245 1 0 $a Design and modeling for 3D ICs and interposers $h [electronic resource] / $c by Madhavan Swaminathan, Ki Jin Han.
260 $a Hackensack, NJ : $b World Scientific $c 2014.
300 $a 1 online resource (200 p.)
490 1 $a WSPC series in advanced integration and packaging ; $v 2
505 0 $a Ch. 1. System integration and modeling concepts. 1.1. Moore's law. 1.2. IC integration vs system integration -- what is the difference? 1.3. History of integration -- an overview. 1.4. Primary drivers for 3D integration. 1.5. Role of the interposer in 3D integration. 1.6. Modeling and simulation. 1.7. Summary -- ch. 2. Modeling of cylindrical interconnections. 2.1. Introduction. 2.2. Specialized basis functions. 2.3. Electric field integral equation (EFIE) with cylindrical CMBF for resistance and inductance extraction. 2.4. Scalar potential integral equation (SPIE) with cylindrical AMBF for conductance and capacitance extraction. 2.5. Broadband equivalent RLC network. 2.6. Inclusion of planar structures. 2.7. Examples with bonding wires. 2.8. Examples with vias. 2.9. Example of package on package. 2.10. Summary -- ch. 3. Electrical modeling of through silicon vias. 3.1. Benefits of through silicon vias. 3.2. Challenges in modeling through silicon vias. 3.3. Propagating modes in through silicon vias -- an electromagnetic perspective. 3.4. Physics based modeling of through silicon vias. 3.5. Rigorous electromagnetic modeling. 3.6. Modeling of conical through silicon via. 3.7. MOS capacitance effect. 3.8. Consideration of MOS capacitance effect in electromagnetic modeling. 3.9. Time domain response. 3.10. Summary -- ch. 4. Electrical performance and signal integrity. 4.1. Process optimization. 4.2. Cross talk in interposers. 4.3. Via arrays. 4.4. Interposers. 4.5. Modeling and design challenges. 4.6. Summary -- ch. 5. Power distribution, return path discontinuities and thermal management. 5.1. Power distribution -- an overview. 5.2. Power distribution for 3D integration. 5.3. Current paths in IC and package. 5.4. Signal and power integrity -- does one affect the other? 5.5. Challenges for addressing power distribution in 3D ICs and interposers. 5.6. Thermal management and its effect on power distribution. 5.7. Summary -- ch. 6. Alternate methods for power distribution. 6.1. Introducing power transmission lines. 6.2. Constant current power transmission line (CCPTL). 6.3. Pseudo balanced power transmission line (PBPTL). 6.4. Constant voltage power transmission line (CVPTL). 6.5. Power calculations. 6.6. Application of power transmission lines to FPGA. 6.7. Managing signal and power integrity for 3D ICs. 6.8. Summary.
520 $a 3D Integration is being touted as the next semiconductor revolution. This book provides a comprehensive coverage on the design and modeling aspects of 3D integration, in particularly, focus on its electrical behavior. Looking from the perspective the silicon via (TSV) and glass via (TGV) technology, the book introduces 3D ICs and Interposers as a technology, and presents its application in numerical modeling, signal integrity, power integrity and thermal integrity. The authors underscored the potential of this technology in design exchange formats and power distribution.
588 $a Description based on print version record.
650 0 $a Three-dimensional integrated circuits. $3 717043
700 1 $a Han, Ki Jin. $3 717042
830 0 $a WSPC series in advanced integration and packaging ; $v v. 1. $3 697656
856 4 0 $u http://www.worldscientific.com/worldscibooks/10.1142/8814#t=toc