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High performance integer arithmetic ...

Chakraborty, Rajat Subhra.

High performance integer arithmetic circuit design on FPGAarchitecture, implementation and design automation /

Record Type:	Electronic resources : Monograph/item
Title/Author:	High performance integer arithmetic circuit design on FPGAby Ayan Palchaudhuri, Rajat Subhra Chakraborty.
Reminder of title:	architecture, implementation and design automation /
Author:	Palchaudhuri, Ayan.
other author:	Chakraborty, Rajat Subhra.
Published:	New Delhi :Springer India :2016.
Description:	xvii, 114 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
Subject:	Field programmable gate arraysComputer-aided design.
Online resource:	http://dx.doi.org/10.1007/978-81-322-2520-1
ISBN:	9788132225201$q(electronic bk.)

High performance integer arithmetic circuit design on FPGAarchitecture, implementation and design automation /
Palchaudhuri, Ayan.

High performance integer arithmetic circuit design on FPGAarchitecture, implementation and design automation /[electronic resource] :by Ayan Palchaudhuri, Rajat Subhra Chakraborty. - New Delhi :Springer India :2016. - xvii, 114 p. :ill., digital ;24 cm. - Springer series in advanced microelectronics,v.511437-0387 ;. - Springer series in advanced microelectronics ;3..

Introduction -- Architecture of Target FPGA Platform -- A Fabric Component based Design Approach for High Performance Integer Arithmetic Circuits -- Architecture of Data path Circuits -- Architecture of Control path Circuits -- Compact FPGA Implementation of Linear Cellular Automata -- Design Automation and Case Studies -- Conclusions and Future Work.

This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs) It explores regular, modular, cascadable, and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary "User Constraints File". The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from user-level specifications. This tool has been used to implement the proposed circuits, as well as hardware implementations of integer arithmetic algorithms where several of the proposed circuits are used as building blocks. Implementation results demonstrate higher performance and superior operand-width scalability for the proposed circuits, with respect to implementations derived through other existing approaches. This book will prove useful to researchers, students, and professionals engaged in the domain of FPGA circuit optimization and implementation.

ISBN: 9788132225201$q(electronic bk.)

Standard No.: 10.1007/978-81-322-2520-1doiSubjects--Topical Terms:

209166
Field programmable gate arrays
--Computer-aided design.

LC Class. No.: TK7895.G36

Dewey Class. No.: 621.395

High performance integer arithmetic circuit design on FPGAarchitecture, implementation and design automation /
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520 $a This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs) It explores regular, modular, cascadable, and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary "User Constraints File". The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from user-level specifications. This tool has been used to implement the proposed circuits, as well as hardware implementations of integer arithmetic algorithms where several of the proposed circuits are used as building blocks. Implementation results demonstrate higher performance and superior operand-width scalability for the proposed circuits, with respect to implementations derived through other existing approaches. This book will prove useful to researchers, students, and professionals engaged in the domain of FPGA circuit optimization and implementation.
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