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Memory controllers for mixed-time-cr...

Goossens, Sven.

Memory controllers for mixed-time-criticality systemsarchitectures, methodologies and trade-offs /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Memory controllers for mixed-time-criticality systemsby Sven Goossens ... [et al.].
Reminder of title:	architectures, methodologies and trade-offs /
other author:	Goossens, Sven.
Published:	Cham :Springer International Publishing :2016.
Description:	xxvii, 202 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
Subject:	Embedded computer systemsProgramming.
Online resource:	http://dx.doi.org/10.1007/978-3-319-32094-6
ISBN:	9783319320946$q(electronic bk.)

Memory controllers for mixed-time-criticality systemsarchitectures, methodologies and trade-offs /
Memory controllers for mixed-time-criticality systemsarchitectures, methodologies and trade-offs /[electronic resource] :by Sven Goossens ... [et al.]. - Cham :Springer International Publishing :2016. - xxvii, 202 p. :ill., digital ;24 cm. - Embedded systems,2193-0155. - Embedded systems..

Introduction -- Reconfigurable Real-Time Memory Controller Architecture -- Memory Patterns -- Cycle-Accurate SDRAM Power Modeling -- Power/Performance Trade-Offs -- Conservative Open-Page Policy -- Reconfiguration -- Related Work -- Conclusions and Future Work -- Appendix A: ILP Problem Formation -- Appendix B: Memory Specifications -- Appendix C: Code Listings -- Appendix D: List of Acronyms -- Appendix E: List of Symbols.

This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.

ISBN: 9783319320946$q(electronic bk.)

Standard No.: 10.1007/978-3-319-32094-6doiSubjects--Topical Terms:

189352
Embedded computer systems
--Programming.

LC Class. No.: TK7895.E42

Dewey Class. No.: 006.22

Memory controllers for mixed-time-criticality systemsarchitectures, methodologies and trade-offs /
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505 0 $a Introduction -- Reconfigurable Real-Time Memory Controller Architecture -- Memory Patterns -- Cycle-Accurate SDRAM Power Modeling -- Power/Performance Trade-Offs -- Conservative Open-Page Policy -- Reconfiguration -- Related Work -- Conclusions and Future Work -- Appendix A: ILP Problem Formation -- Appendix B: Memory Specifications -- Appendix C: Code Listings -- Appendix D: List of Acronyms -- Appendix E: List of Symbols.
520 $a This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.
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