Language:
English
繁體中文
Help
圖資館首頁
Login
Back
Switch To:
Labeled
|
MARC Mode
|
ISBD
Timing performance of nanometer digi...
~
Champac, Victor.
Timing performance of nanometer digital circuits under process variations
Record Type:
Electronic resources : Monograph/item
Title/Author:
Timing performance of nanometer digital circuits under process variationsby Victor Champac, Jose Garcia Gervacio.
Author:
Champac, Victor.
other author:
Garcia Gervacio, Jose.
Published:
Cham :Springer International Publishing :2018.
Description:
xviii, 185 p. :ill., digital ;24 cm.
Contained By:
Springer eBooks
Subject:
NanoelectronicsMaterials.
Online resource:
http://dx.doi.org/10.1007/978-3-319-75465-9
ISBN:
9783319754659$q(electronic bk.)
Timing performance of nanometer digital circuits under process variations
Champac, Victor.
Timing performance of nanometer digital circuits under process variations
[electronic resource] /by Victor Champac, Jose Garcia Gervacio. - Cham :Springer International Publishing :2018. - xviii, 185 p. :ill., digital ;24 cm. - Frontiers in electronic testing,v.390929-1296 ;. - Frontiers in electronic testing ;v.39..
Introduction -- Mathematical Fundamentals -- Process Variations -- Gate delay under process variations -- Path Delay Under Process Variations -- Circuit Analysis under Process Variations -- FinFET Technology and design issues.
This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level "design hints" are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.
ISBN: 9783319754659$q(electronic bk.)
Standard No.: 10.1007/978-3-319-75465-9doiSubjects--Topical Terms:
561110
Nanoelectronics
--Materials.
LC Class. No.: TK7874.84 / .C436 2018
Dewey Class. No.: 621.3815
Timing performance of nanometer digital circuits under process variations
LDR
:02213nmm a2200325 a 4500
001
537795
003
DE-He213
005
20181109161043.0
006
m d
007
cr nn 008maaau
008
190116s2018 gw s 0 eng d
020
$a
9783319754659$q(electronic bk.)
020
$a
9783319754642$q(paper)
024
7
$a
10.1007/978-3-319-75465-9
$2
doi
035
$a
978-3-319-75465-9
040
$a
GP
$c
GP
041
0
$a
eng
050
4
$a
TK7874.84
$b
.C436 2018
072
7
$a
TJFC
$2
bicssc
072
7
$a
TEC008010
$2
bisacsh
082
0 4
$a
621.3815
$2
23
090
$a
TK7874.84
$b
.C449 2018
100
1
$a
Champac, Victor.
$3
814905
245
1 0
$a
Timing performance of nanometer digital circuits under process variations
$h
[electronic resource] /
$c
by Victor Champac, Jose Garcia Gervacio.
260
$a
Cham :
$b
Springer International Publishing :
$b
Imprint: Springer,
$c
2018.
300
$a
xviii, 185 p. :
$b
ill., digital ;
$c
24 cm.
490
1
$a
Frontiers in electronic testing,
$x
0929-1296 ;
$v
v.39
505
0
$a
Introduction -- Mathematical Fundamentals -- Process Variations -- Gate delay under process variations -- Path Delay Under Process Variations -- Circuit Analysis under Process Variations -- FinFET Technology and design issues.
520
$a
This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level "design hints" are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.
650
0
$a
Nanoelectronics
$x
Materials.
$3
561110
650
0
$a
Integrated circuits
$x
Design and construction.
$3
184690
650
0
$a
Radio circuits.
$3
184727
650
1 4
$a
Engineering.
$3
210888
650
2 4
$a
Circuits and Systems.
$3
274416
650
2 4
$a
Processor Architectures.
$3
274498
650
2 4
$a
Electronics and Microelectronics, Instrumentation.
$3
274412
700
1
$a
Garcia Gervacio, Jose.
$3
814906
710
2
$a
SpringerLink (Online service)
$3
273601
773
0
$t
Springer eBooks
830
0
$a
Frontiers in electronic testing ;
$v
v.39.
$3
814907
856
4 0
$u
http://dx.doi.org/10.1007/978-3-319-75465-9
950
$a
Engineering (Springer-11647)
based on 0 review(s)
ALL
電子館藏
Items
1 records • Pages 1 •
1
Inventory Number
Location Name
Item Class
Material type
Call number
Usage Class
Loan Status
No. of reservations
Opac note
Attachments
000000157666
電子館藏
1圖書
電子書
EB TK7874.84 C449 2018
一般使用(Normal)
On shelf
0
1 records • Pages 1 •
1
Multimedia
Multimedia file
http://dx.doi.org/10.1007/978-3-319-75465-9
Reviews
Add a review
and share your thoughts with other readers
Export
pickup library
Processing
...
Change password
Login