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RTL modeling with SystemVerilog for ...

Sutherland, Stuart, (1953-)

RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design /

Record Type:	Language materials, printed : Monograph/item
Title/Author:	RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design /Stuart Sutherland.
remainder title:	RTL modeling with System Verilog for simulation and synthesis using System Verilog for ASIC and FPGA design
Author:	Sutherland, Stuart,
Published:	Tualatin, OR :Sutherland HDL, Inc.,c2017.
Description:	xxxi, 453 p. :ill. ;23 cm.
Subject:	Verilog (Computer hardware description language)
ISBN:	9781546776345 (pbk.) :

RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design /
Sutherland, Stuart,1953-

RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design /RTL modeling with System Verilog for simulation and synthesis using System Verilog for ASIC and FPGA designStuart Sutherland. - Tualatin, OR :Sutherland HDL, Inc.,c2017. - xxxi, 453 p. :ill. ;23 cm.

Includes bibliographical references and index.

ISBN: 9781546776345 (pbk.) :$120Subjects--Topical Terms:

182774
Verilog (Computer hardware description language)

LC Class. No.: TK7885.7 / S966 2017

Dewey Class. No.: 621.392

RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design /
LDR:00822nam a2200217 a 4500 001 549333
003 OCoLC
005 20190801040056.0
007 3cam a2200205 a 450
008 190920s2017 orua b 001 0 eng d
020 $a 9781546776345 (pbk.) : $c $120
020 $a 1546776346 (pbk.)
035 $a (OCoLC)1000614444
035 $a on1000614444
040 $a ORZ $b eng $c ORZ $d OCLCF $d LEATE
050 4 $a TK7885.7 $b S966 2017
082 4 $a 621.392
100 1 $a Sutherland, Stuart, $d 1953- $e author. $3 829305
245 1 0 $a RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design / $c Stuart Sutherland.
246 3 $a RTL modeling with System Verilog for simulation and synthesis using System Verilog for ASIC and FPGA design
260 $a Tualatin, OR : $b Sutherland HDL, Inc., $c c2017.
300 $a xxxi, 453 p. : $b ill. ; $c 23 cm.
504 $a Includes bibliographical references and index.
650 0 $a Verilog (Computer hardware description language) $3 182774
650 0 $a Electronic digital computers $x Design and construction. $3 190470
650 0 $a Computer simulation. $3 182122