國立高雄大學圖資館 |

語系: 繁體中文

說明(常見問題)

圖資館首頁

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

Multi-run memory tests for pattern s...

Mrozek, Ireneusz.

Multi-run memory tests for pattern sensitive faults

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Multi-run memory tests for pattern sensitive faultsby Ireneusz Mrozek.
作者:	Mrozek, Ireneusz.
出版者:	Cham :Springer International Publishing :2019.
面頁冊數:	x, 135 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
標題:	Semiconductor storage devicesTesting.
電子資源:	http://dx.doi.org/10.1007/978-3-319-91204-2
ISBN:	9783319912042$q(electronic bk.)

Multi-run memory tests for pattern sensitive faults
Mrozek, Ireneusz.

Multi-run memory tests for pattern sensitive faults[electronic resource] /by Ireneusz Mrozek. - Cham :Springer International Publishing :2019. - x, 135 p. :ill., digital ;24 cm.

Introduction to digital memory -- Basics of functional RAM testing -- Multi-cell faults -- Controlled random testing -- Multi-run tests based on background changing -- Multi-run tests based on address changing -- Multiple controlled random testing -- Pseudo exhaustive testing based on march tests -- Conclusion.

This book describes efficient techniques for production testing as well as for periodic maintenance testing (specifically in terms of multi-cell faults) in modern semiconductor memory. The author discusses background selection and address reordering algorithms in multi-run transparent march testing processes. Formal methods for multi-run test generation and many solutions to increase their efficiency are described in detail. All methods presented ideas are verified by both analytical investigations and numerical simulations. Provides the first book related exclusively to the problem of multi-cell fault detection by multi-run tests in memory testing process; Presents practical algorithms for design and implementation of efficient multi-run tests; Demonstrates methods verified by analytical and experimental investigations.

ISBN: 9783319912042$q(electronic bk.)

Standard No.: 10.1007/978-3-319-91204-2doiSubjects--Topical Terms:

345116
Semiconductor storage devices
--Testing.

LC Class. No.: TK7895.M4

Dewey Class. No.: 621.38152

Multi-run memory tests for pattern sensitive faults
LDR:02067nmm a2200313 a 4500 001 551401
003 DE-He213
005 20180706162206.0
006 m d
007 cr nn 008maaau
008 191024s2019 gw s 0 eng d
020 $a 9783319912042$q(electronic bk.)
020 $a 9783319912035$q(paper)
024 7 $a 10.1007/978-3-319-91204-2 $2 doi
035 $a 978-3-319-91204-2
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7895.M4
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 621.38152 $2 23
090 $a TK7895.M4 $b M939 2019
100 1 $a Mrozek, Ireneusz. $3 831489
245 1 0 $a Multi-run memory tests for pattern sensitive faults $h [electronic resource] / $c by Ireneusz Mrozek.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2019.
300 $a x, 135 p. : $b ill., digital ; $c 24 cm.
505 0 $a Introduction to digital memory -- Basics of functional RAM testing -- Multi-cell faults -- Controlled random testing -- Multi-run tests based on background changing -- Multi-run tests based on address changing -- Multiple controlled random testing -- Pseudo exhaustive testing based on march tests -- Conclusion.
520 $a This book describes efficient techniques for production testing as well as for periodic maintenance testing (specifically in terms of multi-cell faults) in modern semiconductor memory. The author discusses background selection and address reordering algorithms in multi-run transparent march testing processes. Formal methods for multi-run test generation and many solutions to increase their efficiency are described in detail. All methods presented ideas are verified by both analytical investigations and numerical simulations. Provides the first book related exclusively to the problem of multi-cell fault detection by multi-run tests in memory testing process; Presents practical algorithms for design and implementation of efficient multi-run tests; Demonstrates methods verified by analytical and experimental investigations.
650 0 $a Semiconductor storage devices $x Testing. $3 345116
650 0 $a Computer storage devices $x Testing. $3 345117
650 0 $a Random access memory $x Testing. $3 185576
650 1 4 $a Engineering. $3 210888
650 2 4 $a Circuits and Systems. $3 274416
650 2 4 $a Processor Architectures. $3 274498
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 274412
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-3-319-91204-2
950 $a Engineering (Springer-11647)