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Multi-run memory tests for pattern s...

Mrozek, Ireneusz.

Multi-run memory tests for pattern sensitive faults

Record Type:	Electronic resources : Monograph/item
Title/Author:	Multi-run memory tests for pattern sensitive faultsby Ireneusz Mrozek.
Author:	Mrozek, Ireneusz.
Published:	Cham :Springer International Publishing :2019.
Description:	x, 135 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
Subject:	Semiconductor storage devicesTesting.
Online resource:	http://dx.doi.org/10.1007/978-3-319-91204-2
ISBN:	9783319912042$q(electronic bk.)

Multi-run memory tests for pattern sensitive faults
Mrozek, Ireneusz.

Multi-run memory tests for pattern sensitive faults[electronic resource] /by Ireneusz Mrozek. - Cham :Springer International Publishing :2019. - x, 135 p. :ill., digital ;24 cm.

Introduction to digital memory -- Basics of functional RAM testing -- Multi-cell faults -- Controlled random testing -- Multi-run tests based on background changing -- Multi-run tests based on address changing -- Multiple controlled random testing -- Pseudo exhaustive testing based on march tests -- Conclusion.

This book describes efficient techniques for production testing as well as for periodic maintenance testing (specifically in terms of multi-cell faults) in modern semiconductor memory. The author discusses background selection and address reordering algorithms in multi-run transparent march testing processes. Formal methods for multi-run test generation and many solutions to increase their efficiency are described in detail. All methods presented ideas are verified by both analytical investigations and numerical simulations. Provides the first book related exclusively to the problem of multi-cell fault detection by multi-run tests in memory testing process; Presents practical algorithms for design and implementation of efficient multi-run tests; Demonstrates methods verified by analytical and experimental investigations.

ISBN: 9783319912042$q(electronic bk.)

Standard No.: 10.1007/978-3-319-91204-2doiSubjects--Topical Terms:

345116
Semiconductor storage devices
--Testing.

LC Class. No.: TK7895.M4

Dewey Class. No.: 621.38152

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505 0 $a Introduction to digital memory -- Basics of functional RAM testing -- Multi-cell faults -- Controlled random testing -- Multi-run tests based on background changing -- Multi-run tests based on address changing -- Multiple controlled random testing -- Pseudo exhaustive testing based on march tests -- Conclusion.
520 $a This book describes efficient techniques for production testing as well as for periodic maintenance testing (specifically in terms of multi-cell faults) in modern semiconductor memory. The author discusses background selection and address reordering algorithms in multi-run transparent march testing processes. Formal methods for multi-run test generation and many solutions to increase their efficiency are described in detail. All methods presented ideas are verified by both analytical investigations and numerical simulations. Provides the first book related exclusively to the problem of multi-cell fault detection by multi-run tests in memory testing process; Presents practical algorithms for design and implementation of efficient multi-run tests; Demonstrates methods verified by analytical and experimental investigations.
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