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Embedded deep learningalgorithms, ar...

Bankman, Daniel.

Embedded deep learningalgorithms, architectures and circuits for always-on neural network processing /

Record Type:	Electronic resources : Monograph/item
Title/Author:	Embedded deep learningby Bert Moons, Daniel Bankman, Marian Verhelst.
Reminder of title:	algorithms, architectures and circuits for always-on neural network processing /
Author:	Moons, Bert.
other author:	Bankman, Daniel.
Published:	Cham :Springer International Publishing :2019.
Description:	xvi, 206 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
Subject:	EducationData processing.
Online resource:	https://doi.org/10.1007/978-3-319-99223-5
ISBN:	9783319992235$q(electronic bk.)

Embedded deep learningalgorithms, architectures and circuits for always-on neural network processing /
Moons, Bert.

Embedded deep learningalgorithms, architectures and circuits for always-on neural network processing /[electronic resource] :by Bert Moons, Daniel Bankman, Marian Verhelst. - Cham :Springer International Publishing :2019. - xvi, 206 p. :ill., digital ;24 cm.

Chapter 1 Embedded Deep Neural Networks -- Chapter 2 Optimized Hierarchical Cascaded Processing -- Chapter 3 Hardware-Algorithm Co-optimizations -- Chapter 4 Circuit Techniques for Approximate Computing -- Chapter 5 ENVISION: Energy-Scalable Sparse Convolutional Neural Network Processing -- Chapter 6 BINAREYE: Digital and Mixed-signal Always-on Binary Neural Network Processing -- Chapter 7 Conclusions, contributions and future work.

This book covers algorithmic and hardware implementation techniques to enable embedded deep learning. The authors describe synergetic design approaches on the application-, algorithmic-, computer architecture-, and circuit-level that will help in achieving the goal of reducing the computational cost of deep learning algorithms. The impact of these techniques is displayed in four silicon prototypes for embedded deep learning. Gives a wide overview of a series of effective solutions for energy-efficient neural networks on battery constrained wearable devices; Discusses the optimization of neural networks for embedded deployment on all levels of the design hierarchy - applications, algorithms, hardware architectures, and circuits - supported by real silicon prototypes; Elaborates on how to design efficient Convolutional Neural Network processors, exploiting parallelism and data-reuse, sparse operations, and low-precision computations; Supports the introduced theory and design concepts by four real silicon prototypes. The physical realization's implementation and achieved performances are discussed elaborately to illustrated and highlight the introduced cross-layer design concepts.

ISBN: 9783319992235$q(electronic bk.)

Standard No.: 10.1007/978-3-319-99223-5doiSubjects--Topical Terms:

207353
Education
--Data processing.

LC Class. No.: LB1065 / .M666 2019

Dewey Class. No.: 370.1523

Embedded deep learningalgorithms, architectures and circuits for always-on neural network processing /
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505 0 $a Chapter 1 Embedded Deep Neural Networks -- Chapter 2 Optimized Hierarchical Cascaded Processing -- Chapter 3 Hardware-Algorithm Co-optimizations -- Chapter 4 Circuit Techniques for Approximate Computing -- Chapter 5 ENVISION: Energy-Scalable Sparse Convolutional Neural Network Processing -- Chapter 6 BINAREYE: Digital and Mixed-signal Always-on Binary Neural Network Processing -- Chapter 7 Conclusions, contributions and future work.
520 $a This book covers algorithmic and hardware implementation techniques to enable embedded deep learning. The authors describe synergetic design approaches on the application-, algorithmic-, computer architecture-, and circuit-level that will help in achieving the goal of reducing the computational cost of deep learning algorithms. The impact of these techniques is displayed in four silicon prototypes for embedded deep learning. Gives a wide overview of a series of effective solutions for energy-efficient neural networks on battery constrained wearable devices; Discusses the optimization of neural networks for embedded deployment on all levels of the design hierarchy - applications, algorithms, hardware architectures, and circuits - supported by real silicon prototypes; Elaborates on how to design efficient Convolutional Neural Network processors, exploiting parallelism and data-reuse, sparse operations, and low-precision computations; Supports the introduced theory and design concepts by four real silicon prototypes. The physical realization's implementation and achieved performances are discussed elaborately to illustrated and highlight the introduced cross-layer design concepts.
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