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FPGA-BASED hardware accelerators

Skliarova, Iouliia.

FPGA-BASED hardware accelerators

Record Type:	Electronic resources : Monograph/item
Title/Author:	FPGA-BASED hardware acceleratorsby Iouliia Skliarova, Valery Sklyarov.
Author:	Skliarova, Iouliia.
other author:	Sklyarov, Valery.
Published:	Cham :Springer International Publishing :2019.
Description:	xvi, 245 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
Subject:	Field programmable gate arrays.
Online resource:	https://doi.org/10.1007/978-3-030-20721-2
ISBN:	9783030207212$q(electronic bk.)

FPGA-BASED hardware accelerators
Skliarova, Iouliia.

FPGA-BASED hardware accelerators[electronic resource] /by Iouliia Skliarova, Valery Sklyarov. - Cham :Springer International Publishing :2019. - xvi, 245 p. :ill., digital ;24 cm. - Lecture notes in electrical engineering,v.5661876-1100 ;. - Lecture notes in electrical engineering ;v.132..

Reconfigurable devices and design tools -- Architectures of FPGA-based hardware accelerators and design techniques -- Hardware accelerators for data search -- Hardware accelerators for data sort -- FPGA-based hardware accelerators for selected computational problems -- Hardware/software co-design.

This book suggests and describes a number of fast parallel circuits for data/vector processing using FPGA-based hardware accelerators. Three primary areas are covered: searching, sorting, and counting in combinational and iterative networks. These include the application of traditional structures that rely on comparators/swappers as well as alternative networks with a variety of core elements such as adders, logical gates, and look-up tables. The iterative technique discussed in the book enables the sequential reuse of relatively large combinational blocks that execute many parallel operations with small propagation delays. For each type of network discussed, the main focus is on the step-by-step development of the architectures proposed from initial concepts to synthesizable hardware description language specifications. Each type of network is taken through several stages, including modeling the desired functionality in software, the retrieval and automatic conversion of key functions, leading to specifications for optimized hardware modules. The resulting specifications are then synthesized, implemented, and tested in FPGAs using commercial design environments and prototyping boards. The methods proposed can be used in a range of data processing applications, including traditional sorting, the extraction of maximum and minimum subsets from large data sets, communication-time data processing, finding frequently occurring items in a set, and Hamming weight/distance counters/comparators. The book is intended to be a valuable support material for university and industrial engineering courses that involve FPGA-based circuit and system design.

ISBN: 9783030207212$q(electronic bk.)

Standard No.: 10.1007/978-3-030-20721-2doiSubjects--Topical Terms:

246658
Field programmable gate arrays.

LC Class. No.: TK7895.G36 / S555 2019

Dewey Class. No.: 621.395

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