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Yield-aware analog IC design and opt...

Canelas, Antonio Manuel Lourenco.

Yield-aware analog IC design and optimization in nanometer-scale technologies

Record Type:	Electronic resources : Monograph/item
Title/Author:	Yield-aware analog IC design and optimization in nanometer-scale technologiesby Antonio Manuel Lourenco Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta.
Author:	Canelas, Antonio Manuel Lourenco.
other author:	Guilherme, Jorge Manuel Correia.
Published:	Cham :Springer International Publishing :2020.
Description:	xxiii, 237 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
Subject:	Integrated circuitsDesign and construction.
Online resource:	https://doi.org/10.1007/978-3-030-41536-5
ISBN:	9783030415365$q(electronic bk.)

Yield-aware analog IC design and optimization in nanometer-scale technologies
Canelas, Antonio Manuel Lourenco.

Yield-aware analog IC design and optimization in nanometer-scale technologies[electronic resource] /by Antonio Manuel Lourenco Canelas, Jorge Manuel Correia Guilherme, Nuno Cavaco Gomes Horta. - Cham :Springer International Publishing :2020. - xxiii, 237 p. :ill., digital ;24 cm.

Introduction -- Analog IC Sizing Background -- Yield Estimation Techniques Related Work -- Monte Carlo-Based Yield Estimation New Methodology -- AIDA-C Variation-Aware Circuit Synthesis Tool -- Tests & Results -- Conclusion and Future Work -- Index.

This book presents a new methodology with reduced time impact to address the problem of analog integrated circuit (IC) yield estimation by means of Monte Carlo (MC) analysis, inside an optimization loop of a population-based algorithm. The low time impact on the overall optimization processes enables IC designers to perform yield optimization with the most accurate yield estimation method, MC simulations using foundry statistical device models considering local and global variations. The methodology described by the authors delivers on average a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. In addition to describing a newly developed yield estimation technique, the authors also provide detailed background on automatic analog IC sizing and optimization. Describes a new yield estimation methodology to reduce the time impact caused by Monte Carlo simulations, enabling its adoption in analog integrated circuits sizing and optimization processes with population-based algorithms; Enables designers to reduce the number of redesign iterations, by considering the robustness of solutions at early stages of the analog IC design flow; Includes detailed background on automatic analog IC sizing and optimization.

ISBN: 9783030415365$q(electronic bk.)

Standard No.: 10.1007/978-3-030-41536-5doiSubjects--Topical Terms:

184690
Integrated circuits
--Design and construction.

LC Class. No.: TK7874 / .C364 2020

Dewey Class. No.: 621.3815

Yield-aware analog IC design and optimization in nanometer-scale technologies
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505 0 $a Introduction -- Analog IC Sizing Background -- Yield Estimation Techniques Related Work -- Monte Carlo-Based Yield Estimation New Methodology -- AIDA-C Variation-Aware Circuit Synthesis Tool -- Tests & Results -- Conclusion and Future Work -- Index.
520 $a This book presents a new methodology with reduced time impact to address the problem of analog integrated circuit (IC) yield estimation by means of Monte Carlo (MC) analysis, inside an optimization loop of a population-based algorithm. The low time impact on the overall optimization processes enables IC designers to perform yield optimization with the most accurate yield estimation method, MC simulations using foundry statistical device models considering local and global variations. The methodology described by the authors delivers on average a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. In addition to describing a newly developed yield estimation technique, the authors also provide detailed background on automatic analog IC sizing and optimization. Describes a new yield estimation methodology to reduce the time impact caused by Monte Carlo simulations, enabling its adoption in analog integrated circuits sizing and optimization processes with population-based algorithms; Enables designers to reduce the number of redesign iterations, by considering the robustness of solutions at early stages of the analog IC design flow; Includes detailed background on automatic analog IC sizing and optimization.
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