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A pipelined multi-core machine with ...
~
Lutsyk, Petro.
A pipelined multi-core machine with operating system supporthardware implementation and correctness proof /
Record Type:
Electronic resources : Monograph/item
Title/Author:
A pipelined multi-core machine with operating system supportby Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul.
Reminder of title:
hardware implementation and correctness proof /
Author:
Lutsyk, Petro.
other author:
Oberhauser, Jonas.
Published:
Cham :Springer International Publishing :2020.
Description:
xv, 628 p. :ill., digital ;24 cm.
Contained By:
Springer eBooks
Subject:
Multiprogramming (Electronic computers)
Online resource:
https://doi.org/10.1007/978-3-030-43243-0
ISBN:
9783030432430$q(electronic bk.)
A pipelined multi-core machine with operating system supporthardware implementation and correctness proof /
Lutsyk, Petro.
A pipelined multi-core machine with operating system support
hardware implementation and correctness proof /[electronic resource] :by Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul. - Cham :Springer International Publishing :2020. - xv, 628 p. :ill., digital ;24 cm. - Lecture notes in computer science,99990302-9743 ;. - Lecture notes in computer science ;4891..
Introductory material -- on hierarchical hardware design -- hardware library -- basic processor design -- pipelining -- cache memory systems -- interrupt mechanism -- self modification, instruction buffer and nondeterministic ISA -- memory management units -- store buffers -- multi-core processors -- advanced programmable interrupt controllers (APICs) -- adding a disk -- I/O apic.
ISBN: 9783030432430$q(electronic bk.)
Standard No.: 10.1007/978-3-030-43243-0doiSubjects--Topical Terms:
200322
Multiprogramming (Electronic computers)
LC Class. No.: QA76.6 / .L887 2020
Dewey Class. No.: 005.434
A pipelined multi-core machine with operating system supporthardware implementation and correctness proof /
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hardware implementation and correctness proof /
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Introductory material -- on hierarchical hardware design -- hardware library -- basic processor design -- pipelining -- cache memory systems -- interrupt mechanism -- self modification, instruction buffer and nondeterministic ISA -- memory management units -- store buffers -- multi-core processors -- advanced programmable interrupt controllers (APICs) -- adding a disk -- I/O apic.
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Computer Science (Springer-11645)
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EB QA76.6 .L974 2020 2020
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1 records • Pages 1 •
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https://doi.org/10.1007/978-3-030-43243-0
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